DCD’s RV64IMZicsr RISC-V Core
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core Family this unique CPU offers:
- five-stage pipeline,
- Harvard architecture,
- flexible size of program and data memory together with their allocation in address space.
To give you freedom of choice, you can easily select the CPU interface:
The DRV64IMZicsr was developed as ISO26262 Safety Element out of Context (SEooC) and is technology independent, and compatible with all FPGA and ASIC vendors. As we believe in DCD that one CPU is not enough… you can easily use it with a wide range of DCD’s peripherals, including DMA, SPI, UART, PWM, CAN, and more. These unique features make DRV64IMZicsr core a good choice for many applications like e.g.
- Internet of Things,
- Consumer Electronics
- and many more.
The DRV64IMZicsr is 64-bit core with 32 General Purpose Registers. It performs arithmetic and logic instructions, loads, stores, conditional branches, and unconditional jumps. What’s more, proper usage of base instructions provides an additional set of pseudo instructions which are available in the RISC-V assembly language. The M extension enables the usage of additional integer multiplication and division instructions due to Multiplication and Division unit which is responsible for handling these instructions. The Zicsr extension provides the means to access Control and Status Registers which in turn enables interrupt and exception handling according to version 20211203 of The RISC-V Instruction Set Manual Volume II: Privileged Architecture. With Zicsr extension DRV64IMZicsr core is also equipped with performance counters and timers. External Debug support utilizes JTAG debug interface and is implemented with conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0. That allows core debugging with all tools compatible with this specification available on the market.
The DRV64IMZicsr core is delivered with fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.
- Five‐stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
- M extension
- Zicsr extension
- External Debug support
- JTAG debug interface
- Conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0
- Highly configurable, including:
- Flexible memory size and allocation
- Interface selection: AXI, AHB, Native
- M privilege level support
- Interrupt and exception handling
- Performance counters and timer
- Wide range of supported peripherals, including:
- and more
- Developed as ISO26262 Safety Element out of Context (SEooC)
- Technology independent HDL Source Code
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