DRV64IMZicsr

DRV64IMZicsr – 64-bit RISC-V CPU IP Core

The DRV64IMZicsr is a high-performance 64-bit RISC-V CPU IP core implementing the RV64IM base architecture with M (Multiply/Divide) and Zicsr (Control and Status Registers) extensions, complemented by External Debug support via JTAG. As part of DCD-SEMI’s DRVX RISC-V Core Family, the DRV64IMZicsr is designed for scalable, safety-critical, and long-lifecycle SoC applications.

The core features a five-stage pipeline and Harvard architecture, delivering efficient instruction throughput, predictable execution, and suitability for real-time embedded systems. Flexible configuration of program and data memory sizes, along with customizable address space allocation, allows the processor to be precisely tailored to specific FPGA or ASIC designs.

Performance and Efficiency

Performance scales with configuration, offering up to:

• 1.26 DMIPS/MHz (Dhrystone)

• 2.02 CoreMark/MHz

This balance of performance and area efficiency makes the DRV64IMZicsr well suited for compute-intensive embedded workloads while maintaining tight silicon budgets.

Interfaces and SoC Integration

To simplify integration across diverse platforms, the DRV64IMZicsr supports multiple industry-standard CPU interfaces:

• AXI

• AHB

• Native

The core is technology-independent and compatible with all major FPGA and ASIC vendors, enabling reuse across multiple process nodes and product generations.

Safety, Debug, and Architecture Features

Developed as an ISO 26262 Safety Element out of Context (SEooC), the DRV64IMZicsr is suitable for safety-oriented designs, including automotive and industrial systems.

The CPU implements 32 general-purpose registers and supports arithmetic and logic operations, loads, stores, branches, and jumps. The M extension provides hardware-accelerated integer multiplication and division, while the Zicsr extension enables full access to Control and Status Registers for:

• Interrupt and exception handling

• Performance counters

• Timers

All in compliance with RISC-V Privileged Architecture Specification v20211203.

External Debug support is provided through a JTAG interface, fully compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, ensuring compatibility with widely available commercial and open-source RISC-V debug tools.

Ecosystem and Applications

The DRV64IMZicsr integrates seamlessly with DCD-SEMI’s peripheral IP ecosystem, including DMA, SPI, UART, PWM, CAN, and more, enabling rapid development of complete SoC platforms.

Typical application areas include:

• Automotive

• Industrial and Embedded Systems

• Internet of Things (IoT)

• Consumer Electronics

Verification and Delivery

To reduce integration risk and accelerate time-to-market, the DRV64IMZicsr is delivered with a fully automated testbench and a comprehensive regression test suite, enabling straightforward validation throughout the entire SoC design and verification flow.

DRV32 vs DRV64 – RISC-V CPU Selection Guide (Engineering View)

Choosing between a 32-bit and 64-bit RISC-V CPU is primarily driven by software requirements, address space, performance headroom, and long-term scalability rather than raw DMIPS alone.

Choose DRV32 (32-bit RISC-V) if:

• Your application uses ≤ 4 GB address space

• Software stack is RTOS-based, bare-metal, or lightweight embedded Linux

• Deterministic real-time behavior and low area/power are critical

• You are replacing ARM Cortex-M / legacy 32-bit MCUs

• Automotive or industrial safety applications require tight control and simplicity

Typical use cases

• Automotive body & gateway controllers

• Industrial control and PLC subsystems

• IoT edge devices

• Safety MCUs and companion processors

Key advantages

• Smaller silicon footprint

• Lower power consumption

• Faster bring-up for embedded firmware teams

• Excellent real-time predictability

Choose DRV64 (64-bit RISC-V) if:

• You need large memory addressing (>4 GB)

• Running embedded Linux, hypervisors, or rich OS stacks

• Higher computational throughput per core is required

• Long-lifecycle platforms demand future software scalability

• Consolidation of multiple 32-bit cores into one CPU is desired

Typical use cases

• Automotive domain controllers

• Industrial edge computing

• Smart gateways and AI pre-processing

• Complex SoCs with mixed-criticality workloads

Key advantages

• Native 64-bit addressing and data paths

• Better fit for Linux and advanced middleware

• Higher performance headroom

• Platform longevity and software reuse

Quick Recommendation

If your system behaves like an MCU → choose DRV32.
If your system behaves like a microprocessor → choose DRV64.

DRVX RISC-V Family Comparison Table

Positioning Summary:

• DRV32IMZicsr
  → Optimized for deterministic embedded control, safety MCUs, and cost-sensitive designs.

• DRV64IMZicsr
  → Designed for scalable, software-rich SoCs requiring long-term performance and memory growth.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Five‐stage pipeline
• Harvard architecture
• RV64I Base RISC-V ISA
• M extension
• Zicsr extension
• External Debug support
• JTAG debug interface
• Conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0
• Highly configurable, including:
  • Flexible memory size and allocation
  • Interface selection: AXI, AHB, Native
• M privilege level support
• Interrupt and exception handling
• Performance counters and timer
• Wide range of supported peripherals, including:
  • DMA
  • SPI
  • UART
  • PWM
  • and more
• Developed as ISO26262 Safety Element out of Context (SEooC)
• Performance:
  • Dhrystone: up to 1,26 DMIPS/MHz
  • Coremark: up to 2,02 CoreMark/MHz