DSHA2-256

The DSHA2-256 - a universal solution which accelerates SHA2-256 hash with HMAC mode.

DSHA2-256 is a high-performance hardware accelerator for the SHA-2/256 hash function, fully compliant with FIPS PUB 180-4. Designed for secure SoCs, FPGAs, and embedded systems, the core connects seamlessly to APB, AHB, and AXI bus architectures, providing a universal plug-and-play hashing solution for modern electronics.

The IP core computes message digests in 256-bit and 224-bit modes, supporting input lengths up to 2⁶⁴–1 bits. Depending on configuration, DSHA2-256 also offers native acceleration for SHA-256 HMAC (Keyed-Hash Message Authentication Code) as defined in RFC 2104, making it ideal for data integrity checks, digital signature protocols, secure communication stacks, and even cryptocurrency-related computations.

Designed for Complex, Preemptive Systems

DSHA2-256 includes a context-swapping mechanism, enabling efficient task preemption in multi-threaded and real-time systems. This feature also supports custom or software-managed HMAC pipelines, giving designers maximum flexibility for security architectures.

Cryptographically Secure, Proven Architecture

SHA-2 is a family of one-way compression functions built on the Merkle–Damgård structure. The SHA-256 variant processes 512-bit data blocks across 64 rounds and outputs a fixed 256-bit or 224-bit digest. Because reversing the digest is computationally infeasible, SHA-256 provides 128-bit security (112-bit for SHA-224), making it a trusted standard for secure boot, firmware validation, authentication protocols, and integrity verification.

For applications requiring proof of key possession, DSHA2-256 supports HMAC, combining secret-key operations with SHA-256 hashing to deliver strong, standardized message authentication.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

• FIPS PUB 180-4 compliant SHA2-256 function
• RFC 2104 compliant HMAC mode native support
• SHA2 224 and 256 bit modes support
• Secure storage for precomputed HMAC keys
• Hash/HMAC context swapping
• Internal, automatic padding module
• Binary message resolution support
• Flexible data read/write modes
• Software support:
  • Software driver with OpenSSL/MbedTLS interface ready
• Applications
  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication
• Available system interface wrappers:
• • • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus