DSHA2-384

The DSHA2-384 - a universal solution that accelerates SHA2-384 hash with HMAC mode.

DSHA2-384 is a high-performance hardware accelerator designed to compute SHA-2/384, SHA-2/256, and SHA-2/224 hash functions in full compliance with FIPS PUB 180-4. With native support for APB, AHB, and AXI bus interfaces, it offers a universal, plug-and-play solution for secure SoCs, FPGA platforms, and embedded systems requiring fast and reliable message digest generation.

The core supports input message lengths up to 2⁶⁴ – 1 bits and can optionally accelerate SHA-384 HMAC operations (RFC 2104), enabling robust message authentication for digital signatures, secure communication protocols, firmware integrity checks, and cryptographic workflows. Its high throughput also makes it suitable for accelerating selected cryptocurrency computations.

Optimized for Complex, Preemptive Embedded Architectures

DSHA2-384 includes an advanced context-swapping mechanism, allowing efficient hash computation in systems with task preemption, multi-threaded workloads, or custom HMAC schemes. Engineers can offload hashing tasks to dedicated hardware while maintaining deterministic performance and minimal CPU involvement.

Proven Cryptographic Foundations

SHA-2 is a family of secure one-way compression functions based on the Merkle–Damgård structure.
SHA-384 processes 1024-bit blocks across 80 rounds, producing a fixed 384-bit digest. SHA-256 and SHA-224 operate on 512-bit blocks over 64 rounds with 256- and 224-bit outputs.

Because SHA-2 digests cannot be feasibly inverted, the DSHA2-384 core provides strong one-way security guarantees. SHA-384 delivers 128-bit security, making it a trusted choice for:

• Digital signature verification

• Secure boot

• Data integrity validation

• Key exchange mechanisms

• Authentication via HMAC

By combining a secret key with the SHA-384 or SHA-256 hash function, the hardware-accelerated HMAC mode enables strong, tamper-resistant authentication suitable for mission-critical embedded applications.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• FIPS PUB 180-4 compliant SHA2-256 function
• RFC 2104 compliant HMAC mode native support
• SHA2 224 and 256 bit modes support
• Secure storage for precomputed HMAC keys
• Hash/HMAC context swapping
• Internal, automatic padding module
• Binary message resolution support
• Flexible data read/write modes
• Software support:
  • Software driver with OpenSSL/MbedTLS interface ready
• Applications
  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication
• Available system interface wrappers:
• • • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus