DSHA2-512

The DSHA2-512 - a universal solution that accelerates SHA2-512 hash with HMAC mode.

DSHA2-512 is a high-performance hardware accelerator designed to compute SHA-2/512, SHA-2/384, SHA-2/256, and SHA-2/224 hash functions in full compliance with FIPS PUB 180-4. Featuring native support for APB, AHB, and AXI bus interfaces, it provides a universal, drop-in solution for secure SoCs, FPGA platforms, and embedded systems requiring fast, deterministic, and energy-efficient message digest generation.

The core supports input messages up to 2⁶⁴ – 1 bits and can optionally accelerate HMAC-SHA-512 (RFC 2104), enabling strong message authentication for digital signature workflows, secure communication protocols, firmware integrity checks, and other cryptographic pipelines. Its high throughput also makes it suitable for selected cryptocurrency-related computations.

Designed for Complex, Preemptive Embedded Architectures

DSHA2-512 integrates a hardware context-swapping mechanism, making it ideal for multi-tasking environments, RTOS-based systems, and applications with frequent task preemption. It can also be used in custom or software-managed HMAC implementations, giving system architects maximum control over authentication schemes and performance tuning.

Cryptographically Proven Hash Engine

SHA-2 is a family of secure one-way compression functions based on the Merkle–Damgård construction.

• SHA-512 processes 1024-bit blocks over 80 rounds, producing a fixed 512-bit digest.

• SHA-384, SHA-256, and SHA-224 offer additional output lengths for different security and performance profiles.

The DSHA2-512 core provides strong, hardware-validated one-way security—making it computationally infeasible to recover the original message from its digest. SHA-512 delivers 128-bit cryptographic strength, ensuring suitability for:

• Secure boot and firmware validation

• Digital signature protocols

• Integrity and authenticity verification

• Key-exchange mechanisms

• HMAC-based authentication

By combining a secret key with the SHA-512 function, the hardware-accelerated HMAC mode offers robust, tamper-resistant authentication for mission-critical embedded and edge devices.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

• FIPS PUB 180-4 compliant SHA2-512 function
• RFC 2104 compliant HMAC mode native support
• SHA2 224, 256, 384 and 512-bit modes support
• Secure storage for precomputed HMAC keys
• Hash/HMAC context swapping
• Internal, automatic padding module
• Binary message resolution support
• Flexible data read/write modes
• Software support:
  • Software driver with OpenSSL/MbedTLS interface ready
• Applications
  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication
• Available system interface wrappers:
• • • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus