DSMART

DSMART IP Core – Smart Card Interface Controller for FPGA & ASIC

The DSMART IP Core from DCD-SEMI is a fast, versatile, and cost-efficient smart card reader controller designed for FPGA and ASIC implementations. Acting as a scalable bridge to APB, AHB, and AXI bus architectures, DSMART provides a complete hardware interface for smart cards compliant with ISO 7816-3 and EMV 4.2 / 4.3 standards.

The core implements full hardware support for both major smart card communication protocols:

• T=0 – character-oriented protocol

• T=1 – block-oriented protocol

DSMART is optimized for low CPU utilization and minimal silicon area, making it well suited for secure embedded systems and high-volume designs.

Complete Smart Card Lifecycle Management

DSMART handles the full smart card operation sequence in hardware, including:

• Card activation and deactivation

• Cold and warm reset

• ATR (Answer To Reset) reception and decoding

• Automatic convention detection and decoding

The automatic convention handling ensures correct operation regardless of direct or inverse convention, eliminating software complexity.

Timing, Clocking, and Power Management

The core automatically decodes the Elementary Time Unit (ETU) from the ATR interface bytes and generates the correct bit timing internally. A programmable card clock divider delivers a non-gated clock with a wide frequency range.

A dedicated power-down mode is available, holding the card clock in one of two defined states according to card parameters, enabling low-power operation in secure systems.

High-Performance Data Transfer with DMA Support

Data transfer between the smart card and host system can be performed using:

• Interrupt-driven operation

• Direct Memory Access (DMA)

Optional hardware features include:

• CRC/LRC generation and checking (convention-independent)

• Block length counter for secure DMA transfers

• Automatic or manual CRC/LRC handling

• Dedicated block transfer mode for T=1 protocol

For T=0 protocol, error signaling and character repetition are handled automatically in hardware.

Diagnostics, Status, and Error Reporting

DSMART includes comprehensive status and error registers providing real-time information about:

• FIFO state

• Communication errors

• Card insertion, removal, and event status

The received CRC/LRC is not stored in the FIFO but can be read separately in the event of a CRC/LRC error, ensuring clean data handling.

Integration and Compatibility

DSMART is a technology-independent IP Core that integrates seamlessly into modern SoC designs via:

• AMBA APB interface

• AMBA AHB interface

• AMBA AXI interface

The core works with all major CPU architectures and is 100% compatible with DCD’s MCUs, enabling consistent cryptographic and security implementations across platforms.

Typical Applications

• Smart card readers

• Secure identification systems

• Payment terminals (EMV-compliant)

• Access control and authentication devices

• Secure embedded FPGA and ASIC designs

* Note that DSMART works with all major CPUs and is 100% compatible with DCD’s MCUs – enabling the same – cryptography.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Compatible with the ISO 7816-3: 2006 and EMV 4.2/4.3 standard
• Support for asynchronous Smart Cards
• Dual configurable length FIFO with two programmable thresholds
• Card detection input
• Software-configurable interrupts
• Automatic convention detection and decoding
• Programmable non-gated card clock generator
• Automatic ETU generator
• DMA support for transmit and receive
• Hardware CRC and LRC calculations
• Card power down mode with clock stop high and clock stop low possibility
• Special fast block mode for T1 protocol (optional)
• CRC/LRC hardware generation and checking
• Byte counter with automatic CRC/LRC affixing (optional)
• No tri-state buffers
• Fully synchronous synthesizable design
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus