DSPI

DSPI bridge to APB, AHB, and AXI bus, it is a fully configurable SPI master/slave device, which allows you to configure the polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes the shifting and sampling of information on two independent serial data lines. DSPI data is simultaneously transmitted and received. What’s most important, it’s a technology-independent design that can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. It can be configured as a master or slave device, with data rates as high as CLK/4. Clock control logic allows selecting clock polarity and choosing two fundamentally different clocking protocols, to accommodate the most available synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. The DSPI automatically drives selected by SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and addresses the SPI slave device to exchange serially shifted data. What’s more important, error-detection logic is included, to support interprocessor communications. A write collision detector indicates when an attempt is made to write data to the serial shift register, while the transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master. What does it mean for you? The DSPI is fully customizable, which means, that we deliver it tailored to your configuration and requirements. There is no need to pay extra for unused features and wasted silicon. It includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others. 
• TSMC
• UMC
• SK Hynix
  and others.

• SPI Master
  • Master and Multi-master operations
  • 8 SPI slave select lines
  • System error detection
  • Mode fault error
  • Write collision error
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Bit rates generated 1/4 – 1/512 of system clock.
  • Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers
• SPI Slave
  • Slave operation
  • System error detection
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to microcontrollers
  • Four transfer formats supported
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready