DSPI

DSPI SPI IP Core – High-Performance, Configurable SPI Master/Slave for SoC and FPGA Designs

The DSPI IP Core from DCD-SEMI is a high-performance, fully configurable SPI master/slave controller, bridging seamlessly to APB, AHB, and AXI bus interfaces. Designed for flexible system integration, it allows engineers to configure serial clock (SCK) polarity and phase, enabling robust communication between microcontrollers and serial peripheral devices.

Optimized for multi-master systems, the DSPI controller supports interprocessor communications and simultaneous data transmission and reception on two independent serial data lines. Its technology-independent design allows implementation across a variety of process technologies, making it ideal for FPGA and ASIC integrations.

The DSPI system is compatible with a wide range of peripheral devices from multiple manufacturers. It supports master or slave configurations with data rates of up to CLK/4, and its clock control logic accommodates multiple SPI protocols, ensuring compatibility with most synchronous serial peripherals.

Key features include:

• Automatic Slave Select Control (SSCR) for deterministic device addressing

• Eight selectable SPI clock bit rates for flexible system timing

• Error detection logic supporting interprocessor communications

• Write-collision detection to prevent data corruption during transfers

• Multi-master fault protection automatically disables output drivers if bus contention occurs

• Fully customizable IP delivered tailored to your system configuration, reducing unused features and wasted silicon

The DSPI IP Core includes a complete automated test bench, enabling rapid validation at every stage of the SoC design flow. Its combination of high configurability, reliability, and performance makes it the perfect SPI solution for embedded, SoC, and FPGA-based designs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• SPI Master
  • Master and Multi-master operations
  • 8 SPI slave select lines
  • System error detection
  • Mode fault error
  • Write collision error
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Bit rates generated 1/4 – 1/512 of system clock.
  • Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers
• SPI Slave
  • Slave operation
  • System error detection
  • Interrupt generation
  • Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to microcontrollers
  • Four transfer formats supported
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready