Description

The DSPIS is a fully configurable SPI slave device, designed to operate with passive devices, like memories, LCD drivers etc. It allows you to configure polarity and phase of serial clock signal SCK. A serial clock line (SCK) synchronizes information shifting and sampling on two independent serial data lines. Moreover, data is simultaneously transmitted and received. The DSPIS system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The clock control logic (CLK/4) allows selecting clock polarity and a choosing two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. The DSPIS allows the SPI Master to communicate with passive devices. When transmission starts (SS Line goes low), the first portion of data is copied to the address register and then, to the ADDRESS bus output. After transmission of the address, the DSPIS generates the read signal (RD) and copies DATAI bus contents to the transmitter shift register, and prepares data to be exchanged with the SPI Master. During the next portion of data transmission, the DSPIS simultaneously transfers the data out and in. When the first portion of data is received, the DSPIS asserts DATAO bus generates the write signal (WE), then increments ADDRESS bus performs a read operation and prepare another data portion to be exchanged with SPI master. The transmission is ended when the SS line goes high. The DSPIS is a technology independent design, so can be implemented in variety of process technologies. It’s also fully customizable – the configuration is tailored to your requirements. There is no need to pay extra for unused features and wasted silicon. The DSPIs comes with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

Key features

  • Full duplex synchronous serial data transfer
  • Slave operation
  • Automatic read and write operations
  • Automatic address incrementation after any data portion transfer
  • Configurable address and data length
  • Configurable SCK phase and polarity
  • Supports speeds up 1/4 of system clock
  • Simple interface allows easy connection to passive devices and SPI Master
  • Four transfer formats supported
  • Simple interface allows easy connection to microcontrollers
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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