The DTPCI32DC is a 32-bit target interface which provides all requirements of the PCI 3.0 specification for a target device. It compromises a minimal gate count with a high-bandwidth data transfer. The Core’s main feature is a presence of two clock domains which enable flexibility as well as higher performance. When time required for implementation becomes crucial, the DTPCI32DC brings domain crossing. The time saved can be used for a specific system implementation instead. The user-friendly back-end interface can be very easily and effectively tailored to the design needs. The Core supports up to six Base Address Registers and Expansion Rom address register with both I/O and Memory space decoding from 16 bytes up to 4 GB. Another important feature is a cache wrapping hardware support and cacheline pre-fetching capability. The DTPCI32DC is accepting size cache lines which are powered from 2 up to 128. It enables also target-disconnect with data, without data or by target abort. Moreover, the DTPCI32DC is able to work with 66 MHz clock frequency in most popular technologies. It assures PCI timing requirements as well as other parameters, like FIFOs depths number and Base Address Registers (they can be easily configured at the pre-synthesis stage).

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Key features

  • Fully supports PCI specification 3.0 protocol
  • Stable clock domain crossing regardless of the clock frequencies
  • Cache wrapping (cache lines must be powers of 2)
  • User controlled burst data transfer
  • Possible no-wait state transactions
  • Automatic handling of configuration space read/write access
  • Parity generation and parity error detection
  • Single interrupt support
  • Configurable FIFOs depth
  • Supported backend initiated burst termination (with and without data)
  • No tri-state buffers

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