MS Platform

USB 2.0 Mass Storage IP Core – Complete Design Platform for High-Performance USB Devices

The USB 2.0 Mass Storage Design Platform from DCD-SEMI is a fully integrated, turnkey solution for creating high-performance USB-based mass storage devices. Ideal for applications such as portable flash drives, digital audio players, card readers, and digital cameras, this platform accelerates development and ensures reliable, high-speed data transfer.

Key Features of the USB 2.0 Mass Storage Design Platform:

• DUSB2 Peripheral Controller – Supports 12 Mb/s Full Speed (FS) and 480 Mb/s High Speed (HS) USB 2.0 data transfer rates, enabling fast and efficient communication with host devices.

• DP8051XP Microcontroller – Ultra-high-performance, speed-optimized 8-bit 8051 CPU, fully customizable with integrated DoCD™ debug IP core for streamlined software development and debugging.

• Optimized Mass Storage Software Stack – Designed specifically for the DP8051XP 8-bit microcontroller, providing a ready-to-use software framework for rapid development.

• FPGA Board with Preprogrammed Example – Includes a flash memory device application, allowing developers to test and prototype immediately.

• DoCD™ Hardware Assisted Debugger (HAD2) – Ensures precise debugging capabilities, reducing development time and enhancing reliability.

• DoCD™ Debug Software & Drivers – Fully compatible with Keil and IAR development environments, supporting seamless integration into your design workflow.

This USB 2.0 Mass Storage IP Core is the ideal choice for engineers and developers looking to accelerate USB device development, maximize performance, and ensure reliable high-speed data storage solutions.

Applications:

• Portable USB Flash Drives

• Digital Audio Players (MP3/MP4 devices)

• Card Readers (SD, microSD, CF)

• Digital Cameras and Imaging Devices

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Supports UTMI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• 100% software compatible with industry standard 8051
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
• Up to 16M bytes of external (off-chip) Data Memory
• User programmable Program Memory Wait States solution for wide range of memories speed
• User programmable External Data Memory Wait States solution for wide range of memories speed
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready