Digital Core Design, as a leading IP Core provider and System-on-Chip (SoC) design house, has been invited for a conference “Know-how transfer in automotive”. The conference was held during international Fair of Automation and Robotization in Industry at Expo Silesia, Poland.
Bytom, Poland November 17th, 2011. Digital Core Design as a proprietary automotive IP Core provider participated in fair show and the international conference devoted to know-how transfer. Poland and Silesia Region particularly is one of the leading country regarding to automotive business in Europe. Thanks to the main European FIAT fab and OPEL (General Motors) factory which manufacture their newest car models, growth rate is positive, even though economy crisis. Strict cooperation with concerns propels also proprietary solutions providers. – We noticed that safety & power safe technologies are becoming one of the most significant ones, not only in automotive – says Tomasz Krzyzak, vice-president at Digital Core Design – that’s why not only our CPU solutions but also “automotive” interfaces CAN or LIN are equipped with enhanced control and power safe solutions.
Like for example CAN is a keyword connecting the world of electronics with the world of automotive. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why Digital Core Design developed unique IP Core, which delimits the highest quality standards. The DCAN is a standalone controller for the Controller Area Network (CAN), which is common used in automotive and industrial applications. What’s the most important, DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). The Core has simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies.
More information: http://dcd.pl/ipcore/131/dcan/