Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, introduced the USB HID Design Platform. It is complete and integrated solution which targets almost all aspects of USB based Human Interface Devices. Apart from that, DCD’s solution enhances Internet of Things (IoT) projects thanks to its software stack optimized with ultra-low power DP8051 8.bit CPU.
- DUSB2 peripheral controller, designed to support 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates
- DP8051XP ultra high performance, speed optimized, fully customizable 8051 8-bit microcontroller with built-in DoCDTM debug IP core
- Human Interface Devices software stack optimized for DP8051XP 8-bit CPU
- FPGA board with ready to use, preprogrammed example HID application
- HAD2 – DoCDTM Hardware Assisted Debugger board
- DoCDTM Debug Software
- DoCDTM driver for Keil development software
- DoCDTM driver for IAR development software
Digital Core Design’s USB HID Design Platform is a complete and integrated solution created to enhance USB based Human Interface Devices design experiences. Mouses, keyboards, tablets but also hundreds of other e-quipment is based on stable USB connection. So it’s not a secret that a true programmable embedded system-on-chip integrating configurable analog and digital peripheral functions, is one of the biggest challenges engineers ever faced. – Our Human Interface Devices Design Platform offers the highest level of testability, conformance and verification – explains Tomasz Krzyzak, DCD’s Vice President, Member of the Board of Directors. This specific SoC seems to be the leading combination of all crucial elements implemented in one IP Core.
The USB HID Design Platform supports UTMI Transceiver Macrocell Interface as well as low cost Full Speed Macrocells. It’s been stacked with the DP8051 DCD’s IP Core, which guarantees 100% software compatibleness with ’51 industry standard. The same engineers gets up to 256 bytes of internal (on chip) Data Memory, up to 64K bytes of internal (on chip) or external (off chip) Program Memory. Last but not least, along with up to 16M bytes of external (off chip) Data Memory, goes a programmable Program Memory Wait States for wide range of memories speed.
More information http://dcd.pl/ipcore/93/hid-platform/