IP Core provider and System-on-Chip design house from Poland introduced the DI3CM-FIFO IP Core. It incorporates all features required by the latest MIPI I3C specification. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance.
Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. – The DI3CM-FIFO offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems – explains Piotr Kandora, Vice President of Digital Core Design.
The I3C interface uses an I2C-like interface with data line (SDA) and clock line (SCL). The open drain SDA line allows for slaves to take control of the data bus and initiate interrupts. The push-pull SCL line is used by the master to clock the communication bus up to 12.5 MHz. The master can dynamically assign 7-bit addresses to all I3C devices while supporting the static addresses of legacy I2C devices. This ensures full compatibility between MIPI I3C and I2C. The Core represents a shift in power performance while providing greater than an order of magnitude improvement in speed over I2C. I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved in each mode are 11.1, 20, 23.5 and 33.3 Mbps, respectively, protected by I3C’s basic error detection mechanisms.
The I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.
- conforms to MIPI I3C v1.0 specifications
- MIPI Manufacturer ID: 0x03B3
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Legacy I2C messaging
- I2C-like Single Data Rate messaging (SDR)
- Master operation with FIFO:
- Master transmitter
- Master receiver
- Supports flexible transmission speed modes:
- FAST-PLUS (up to 1000 kb/s)
- SDR (up to 12,5 Mb/s)
- Configurable FIFO size up to 256 Bytes
- Configurable SDA/SCL glitch filter
- Software programmable SDA/SCL bus timings
- Multi-master systems supported
- Interrupt generation
- Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
- Configurable interface allows easy connection to standard bus interfaces: APB, AHB, 8051, 80251, others
- Support for in-band interrupts
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Command queue support
- Low power management support
- Fully interoperable with third-party I3C master and slave solutions
- Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset