Digital Core Design, IP Core and System on Chip design house from Poland introduced its latest solution – DEEPROM. It performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Moreover, DCD’s IP Core DEEPROM implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.
Digital Core Design, celebrating in 2014 its 15th anniversary introduced newest IP Core which targets DRAM designs. The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. – Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory – says Jacek Hanke, DCD’s CEO. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it’s visible and controlled as parallel SRAM with long access time. – DEEPROM’s big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip – adds Hanke.
When all other factors are sustained, memory controller is becoming crucial. That’s why DCD’s IP Core has been developed to ensure the most accurate data flow. It was designed in accordance with JEDEC specification and all the other industry standards, which summarized together make the DEEPROM very small, efficient, with no internal tri-state buffers and signals IP Core.
More information: http://dcd.pl/ipcore/146/deeprom/
Watch the DEEPROM presentation on You Tube: http://youtu.be/lHbSfQAerlM
DEEPROM’s Key Features:
- Standard memory interface with ready control
- Configurable SPI parameters
- Serial clock prescaler
- SPI mode
- CS hold/setup
- Updating bits in EEPROM status register
- Simple interface allows easy connection to microcontrollers
- Fully synthesizable, static design with no internal tri-states