Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has recently informed about its world’s fastest 8051 & 80251 CPUs. To enable engineers even better experience with these unique solution, the company introduced a non-intrusive hardware debugger for DQ8051 and DQ80251. The system is called DoCDTM (DCD’s on-Chip Debugger) and consists of the Debug IP Core, Hardware Assisted Debugger and Debug Software. It features inter alia instruction smart trace buffer (configurable up to 8192 levels), hardware debugging, software simulation and verification.
DoCDTM provides some serviceable features like a real-time and non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on-chip software debugging. It allows hardware breakpoints, trace, variables watch and multi C sources debugging. – The DoCDTM Debug Software can work as a hardware debugger, as well as a software simulator – explains Tomasz Krzyzak, vice-president at Digital Core Design – some tasks can be validated at software simulation level and after this step, it can continue real-time debugging by uploading code into silicon.
The DoCDTM user can choose favorite C compilers or assemblers for software development – it supports most of High Level Object files produced by C/ASM compiler tools:
- Extended OMF-51 produced by Keil compiler
- IAR EWB 8051 & 80390 workbench
- OMF-51 produced by Tasking compiler
- Standard OMF-51 produced by some 8051 compilers
- Extended OMF-251 produced by Keil compiler
- NOI format file produced by SDCC-51 compiler
- Intel HEX-51 format produced by each 8051 compiler
- Intel HEX-386 format produced by each 80390 & 80251 compiler
- BIN format produced by each 8051 & 80390 & 80251 compiler
System-on-Chip designs are facing a problem of inaccessibility of important control and bus signals, because they often lay behind the physical pins of the device – that makes traditional measurement instrumentation useless. The best way to get around those limitations is to use on-chip debug tools for the tasks verification and software debugging. Other advantage of on-chip debugger is its improved design productivity in an integrated environment, with graphical user’s interface. Ability to display/modify memories’ content, processor’s and peripherals’ register windows, along with information tracing and ability to see the related C/ASM source code, are the key elements, that help to improve the design process and thereby, to increase productivity.
The DoCDTM Hardware Debugger provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows improving size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.
– The reason for the development of the DoCDTM, was to provide our customers with the ability of easy system verification and software debugging, at no additional charges – adds Tomasz Krzyzak from DCD – Therefore, we have decided to add the complete debug system to each 8051/80251/80390 IP Core – for free.
Now DCD’s customers have the exceptional possibility, to obtain the complete solution for mak-ing their own 8051 & 80251 based SoC, with the ability of pre-silicon validation and post-silicon software debugging – in one place. It’s really unusual opportunity for the designer, to have the ability to get a high quality IP Core and unique on-chip debug tool, from the same supplier.
More information: http://dcd.pl/page/154/docd/