The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. – It is a technology-independent design that can be implemented in a variety of process technologies – explains Jacek Hanke, DCD-SEMI CEO.

The DESPI is flexible enough to interface directly with numerous peripherals. The system may be configured either as master or as slave, and depending on the core configuration, the _in or _out lines will be utilized. Its serial clock can run up to 66MHz – adds Hanke.

The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration with the target design requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs, capable of storing up to 4096+16 bytes (Header and maximal data payload) in separate buffers for every eSPI channel. (Peripheral Channel Posted and Non-Posted, Virtual Wire Channel, Out of Band Channel, Flash Access Channel).

Additionally, customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines are also supported. An interesting and unique feature is the Alert mechanism, used by the eSPI Slave to request service from the eSPI master.

The controller is capable to operate in several eSPI configurations:

  • Single Master- Single Slave,
  • Single Master – Multiple Slaves.

The DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. The DCD SPI cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

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