D8259

The D8259 is a soft Core Programmable Interrupt Controller, fully compatible with the 82C59A device. Our efficient IP core can manage up to 8-vectored priority interrupts for the processor. Moreover, you can also program it to cascade and gain up to 64 vectored interrupts. And if it’s not enough, you can always get more than 64 vectored interrupts. Just program our IP Core to the Poll Command Mode. The D8259 can operate in all 82C59A modes and supports all 82C59A features. The D8259 Package includes a fully automated test bench. Thanks to a complete set of tests you can easily validate the whole package at each stage of the SoC design flow. Same as all DCD’s IP Cores, this one’s also got technology independent design which can be implemented in a variety of process technologies.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• 8 vectored priority interrupts
• Up to sixty-four vectored priority interrupts with cascading
• Support for all 82C59A modes features
  • MCS-80/85 and 8088/8086 processor modes
  • Fully nested mode and special fully nested mode
  • Special mask mode
  • Buffered mode
  • Pool command mode
  • Cascade mode with master or slave selection
  • Automatic end-of-interrupt mode
  • Specific and non-specific end-of-interrupt commands
  • Automatic and Specific Rotation
  • Edge and level triggered interrupt input modes
  • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
• Fully synthesizable HDL Source Code
• Static design and no internal tri-states