D8259

D8259 IP Core — Programmable Interrupt Controller for Embedded Systems

High-Performance Soft Core Interrupt Controller

The D8259 IP Core from DCD-SEMI is a soft-core Programmable Interrupt Controller (PIC), fully compatible with the 82C59A industry-standard device. Designed for embedded systems and SoC designs, this efficient IP Core allows engineers to manage up to 8 vectored priority interrupts, with support for cascading to 64 vectored interrupts. For advanced applications, the D8259 can be configured in Poll Command Mode to handle more than 64 vectored interrupts, offering maximum flexibility for complex systems.

Comprehensive Feature Set

The D8259 IP Core supports:

• All 82C59A modes including fully vectored and priority-controlled interrupts

• Cascading capability to expand from 8 to 64 interrupts

• Poll Command Mode for handling extended interrupt counts

• Technology-independent design for FPGA, ASIC, and SoC integration

• Fully automated test bench with complete tests for easy SoC validation

This combination of features ensures reliable, efficient, and flexible interrupt management across modern embedded system architectures.

Why Choose DCD-SEMI D8259 IP Core

• Fully compatible with the 82C59A standard

• Supports up to 8 vectored interrupts, expandable to 64+

• Configurable in all 82C59A modes

• Poll Command Mode for high-interrupt-count applications

• Includes automated test bench for seamless verification

• Technology-independent, suitable for FPGA, ASIC, and SoC designs

• Ideal for embedded microprocessors and complex system designs

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For technical specifications, integration guidance, or custom configurations, contact
info@dcd-semi.com

• 8 vectored priority interrupts
• Up to sixty-four vectored priority interrupts with cascading
• Support for all 82C59A modes features
  • MCS-80/85 and 8088/8086 processor modes
  • Fully nested mode and special fully nested mode
  • Special mask mode
  • Buffered mode
  • Pool command mode
  • Cascade mode with master or slave selection
  • Automatic end-of-interrupt mode
  • Specific and non-specific end-of-interrupt commands
  • Automatic and Specific Rotation
  • Edge and level triggered interrupt input modes
  • Reading of interrupt request register (IIR) and in-service register (ISR) through data bus
• Fully synthesizable HDL Source Code
• Static design and no internal tri-states