DμART UART IP Core – Soft Core UART for FPGA & ASIC

Small is beautiful...
The DμART is one of the tiniest UART IP Cores available on the market.

Description

DμART UART IP Core – High-Performance Soft UART for FPGA & ASIC

The DμART from DCD-SEMI is a soft core Universal Asynchronous Receiver/Transmitter (UART), designed for seamless integration into APB, AHB, and AXI bus architectures. It provides high-efficiency serial communication while minimizing CPU load, making it ideal for both embedded systems and standalone UART implementations.

Efficient Serial-to-Parallel Data Conversion

The DμART performs:

Serial-to-parallel conversion on data received from peripheral devices or MODEMs
Parallel-to-serial conversion for data transmitted from the CPU
Provides complete status information to the CPU, including transfer type, operation status, and error conditions such as overrun and framing

This ensures reliable and predictable UART communication in complex SoC and FPGA designs.

Programmable Baud Rate Generator

The core includes a flexible baud rate generator:

Divides timing reference clock input by divisors of 1 to (2¹⁶–1)
Produces 16× clocks to drive transmitter logic
Can also drive receiver logic, supporting high-precision UART timing

This flexibility allows the DμART to work in synchronous systems with CPU clock alignment or in standalone multi-UART environments.

Advanced Interrupt System

Processor-interrupt system configurable to application requirements
Reduces CPU overhead for data handling and serial communication management
Supports polling or interrupt-driven operation, ideal for low-power or high-throughput designs

Key Features

Soft core UART compatible with ASIC and FPGA designs
Full support for internal CPU interfacing via APB, AHB, or AXI
High-performance serial communication with minimal CPU load
Configurable baud rates and clocking
Error detection for overrun and framing errors
Scalable for standalone or multi-UART systems

Ideal Applications

Embedded systems requiring reliable UART communication
FPGA or ASIC implementations with multiple UART channels
Industrial automation, telecom, and IoT applications
Legacy system replacements where soft UART cores are needed

Verification-Ready and Technology Independent

Like all DCD-SEMI UART cores, DμART comes with:

A fully automated testbench
Complete validation suite for easy SoC integration
Technology-independent design for implementation across multiple FPGA and ASIC processes

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Feature / IP Core	D16450	D16550	D16750	D16752	D16950	D8530	DMESCC	D26C92	DμART
Primary Function	Classic UART	FIFO-based UART	High-performance UART	Dual-channel high-performance UART	High-throughput UART	Dual-channel USART	Dual-channel multiprotocol serial controller	Dual-channel UART / DUART	Lightweight soft UART
UART Compatibility	16450 / TL16C450	16550 / TL16C550A	16750 / TL16C750	16752 / TL16C752	16450–16750 + OX16C950	Zilog 8530–compatible	Enhanced ESCC-compatible	SC26C92 / SCC2692 / SCN2681 compatible	Generic UART / custom soft core
Channels	1	1	1	2	1	2	2	2	1
Supported Modes	Asynchronous	Asynchronous & FIFO	Asynchronous & FIFO	Asynchronous & FIFO, dual-channel	Asynchronous & synchronous	Asynchronous & synchronous	Asynchronous & synchronous	Asynchronous & FIFO, dual-channel	Asynchronous
FIFO Support	❌ No FIFO	✅ 16-byte FIFO	✅ 512-byte FIFO	✅ 64-byte FIFO per channel	✅ 128-byte FIFO	Optional / limited	Optional / configurable	✅ 8-character RX/TX FIFO per channel	❌ No FIFO
FIFO Trigger Levels	—	Configurable	Programmable (1–512)	Programmable per channel	Programmable (1–127)	—	—	Programmable per channel	—
CPU Load	High	Medium	Low	Low	Low	Medium	Medium	Medium	Low
Error Reporting	Parity, framing, overrun, break	Parity, framing, overrun, break	Parity, framing, overrun, break	Parity, framing, overrun, break, idle	Parity, framing, overrun, break	Parity, CRC, abort	Parity, CRC, abort	Parity, framing, overrun, break	Overrun, framing
CRC Generation / Check	No	No	No	No	No	Yes (sync modes)	Yes (sync modes)	No	No
Modem Control	Full	Full	Advanced autoflow	Hardware/software flow control, TCR	Advanced autoflow	Yes (both channels)	Yes (both channels)	Yes, DMA & modem interface	Optional via software
Interrupt System	Programmable	Programmable	Advanced programmable	Programmable, FIFO RDY register	Advanced programmable	Programmable	Programmable	Programmable, independent per channel	Lightweight programmable
DMA Support	Interrupt-optimized	Interrupt-optimized	Yes	Yes	Yes	Yes	Yes	Yes	Optional
Clocking Options	Internal BRG	Internal BRG	Internal / external	Internal / external	Internal / external	Internal BRG	Internal BRG	Independent programmable clock, external or 16× derived	Internal / external programmable
Special Features	Legacy compatibility	Configurable FIFO & Modem	Deep FIFO (512B), autoflow, 16450 modes	Dual-channel, FIFO RDY register, hardware/software flow control, TCR	Deep FIFO, 9-bit mode, synchronous	Legacy protocol support (HDLC, SDLC)	Enhanced block transfer, vectored interrupts	Independent channel baud rates, watchdog timers, dual-speed operation	Lightweight, flexible baud rate, minimal CPU load, standalone or integrated use
Typical Applications	Legacy UART replacement	FIFO-based legacy upgrade	High-throughput UART, legacy replacement	Dual-channel embedded UART, TL16C752 replacement	Telecom, industrial gateways	Telecom, LAN, industrial serial	Communications controllers, protocol engines	Dual-speed terminals, embedded dual UART systems, SC26C92 replacement	Embedded soft UART, low-resource FPGA/ASIC designs
Bus Interfaces	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI
Technology Independence	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes

Selection Guidelines

D16450: Exact legacy 16450 / TL16C450 replacement.
D16550: FIFO buffering and moderate CPU optimization.
D16750: High-performance UART with deep FIFO and low CPU load.
D16752: Dual-channel UART with 64-byte FIFOs, hardware/software flow control, TCR.
D16950: High-throughput UART with deep FIFO, synchronous mode, and advanced flow control.
D8530: Dual-channel USART for legacy protocol support.
DMESCC: Advanced multiprotocol serial communication and block handling.
D26C92: Dual-channel SC26C92 / SCC2692 / SCN2681 replacement with watchdog timers.
DμART: Lightweight soft UART, minimal CPU load, flexible baud rate, ideal for embedded FPGA/ASIC systems.

Watch the DμART presentation on DCD’s You Tube:

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

DUART ASIC
DUART INTEL FPGA
DUART LATTICE
DUART MICROSEMI
DUART XILINX

Key features

Majority Voting Logic
Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from serial data
In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data
Independently controlled transmit, receive, line status, and data set interrupts
16 bit programmable baud generator
False start bit detection
Line break generation and detection. Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Overrun, framing error detection
Full prioritized interrupt system controls
Technology independent HDL Source Code
Fully synthesizable static design with no internal tri-state buffers
Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus

DUART

Small is beautiful... The DμART is one of the tiniest UART IP Cores available on the market.