DCD's Universal Timers System

DUTS IP Core – Universal Timers System for FPGA & ASIC Designs

The DUTS (DCD Universal Timers System) IP Core from DCD-SEMI is a highly programmable and modular timing subsystem designed for FPGA and ASIC implementations. DUTS integrates multiple independent timer and control modules into a single, configurable IP Core, enabling precise time measurement, event counting, PWM generation, and system supervision in modern SoC designs.

The core consists of seven configurable submodules, each of which can operate independently or be excluded entirely to minimize silicon area and power consumption.

Modular Architecture with Fine-Grain Configuration

DUTS includes the following submodules:

• Pulse Width Modulation (PWM)

• Timer 1

• Timer 2

• Timer 3

• Real-Time Interrupt (RTI)

• Computer Operating Properly (COP) watchdog

• Pulse Accumulator (PA)

Unused submodules can be disabled via parameters before synthesis. Additionally, individual Input-Capture or Output-Compare blocks within Timer 1 can be selectively removed, enabling optimal resource utilization.

The core supports switchable native interfaces, allowing designers to choose between 8-bit or 32-bit DUTS interfaces.

PWM Subsystem – Flexible Multi-Channel Control

The PWM module provides up to four 8-bit PWM channels, with channel pairs combinable into 16-bit PWM outputs. Features include:

• Three clock sources (A, B, S) with flexible clock selection

• Configurable channel polarity

• Double-buffered period and duty-cycle registers

• Glitch-free PWM updates during runtime

This makes DUTS suitable for motor control, power management, and LED driving applications.

Timer 1 – Advanced Capture and Compare Engine

Timer 1 is built around a free-running 16-bit counter with a 4-stage programmable prescaler. Key capabilities include:

• Timer overflow extension beyond 16-bit range

• Up to four Input-Capture channels with dedicated 16-bit capture registers

• Up to five Output-Compare channels with individual compare registers

• Fully programmable edge detection and automatic output actions

Each function has separate interrupt control and vector, making Timer 1 ideal for software-driven, real-time control applications.

Timer 2 and Timer 3 – Event Counting and Timing

Timer 2 and Timer 3 each include:

• Prescaler and 16-bit counter

• Three dedicated Output-Compare registers

• One software-selectable Input-Capture or Output-Compare function

• External event counting mode

Like Timer 1, all functions include individual interrupts and programmable control logic, supporting precise time measurement and event tracking.

Real-Time Interrupt (RTI)

The RTI module generates periodic hardware interrupts at one of four fixed rates. It uses a free-running, non-stoppable clock source, ensuring stable and deterministic interrupt timing.

COP Watchdog – System Safety and Reliability

The Computer Operating Properly (COP) module is a watchdog timer that protects the system from software faults. Features include:

• Software-controlled enable/disable

• Configurable clock source

• Scalable watchdog timeout

This ensures reliable operation in safety-critical systems.

Pulse Accumulator – Event and Time Measurement

The Pulse Accumulator (PA) subsystem is based on an 8-bit counter and supports:

• Event counting mode

• Gated time accumulation mode

• Two independent, maskable interrupts with separate vectors

The alternate functions of the PAI pin enable advanced signal measurement use cases.

Typical Applications

• Motor control and power electronics

• Industrial automation and control systems

• Real-time embedded systems

• FPGA-based SoCs requiring complex timing

• ASIC designs with watchdog and event monitoring requirements

Why Choose DUTS Over Discrete Timer Blocks?

Design teams often assemble multiple standalone timer IPs—PWM, capture/compare timers, watchdogs, and real-time interrupts—to meet system requirements. While functional, this approach increases integration effort, verification cost, and silicon overhead.
DUTS provides a single, cohesive Universal Timers System, optimized for performance, scalability, and resource efficiency.

1. System-Level Integration vs. IP Fragmentation

Discrete timers

• Multiple IP blocks with different interfaces

• Separate clocking, resets, and interrupt schemes

• Increased integration and bring-up complexity

DUTS

• Unified architecture with consistent programming model

• Common interrupt structure and control logic

• Faster SoC integration and reduced system risk

Result: Shorter integration time and fewer system-level bugs.

2. Area and Power Optimization

Discrete timers

• Fixed functionality per block

• Redundant prescalers, counters, and registers

• Higher static and dynamic power consumption

DUTS

• Modular submodules (PWM, timers, COP, RTI, PA)

• Unused modules can be fully removed at synthesis

• Fine-grain removal of unused Input-Capture / Output-Compare logic

Result: Lower gate count and power, especially in ASIC designs.

3. Consistent Timing and Interrupt Behavior

Discrete timers

• Different timer resolutions and overflow handling

• Separate interrupt logic and priorities

• Harder to guarantee deterministic timing

DUTS

• Harmonized timer architecture across all submodules

• Independent interrupt vectors with unified control

• Predictable timing behavior across the entire system

Result: Easier real-time analysis and safer system design.

4. Software Efficiency and Maintainability

Discrete timers

• Multiple driver models and APIs

• Higher software maintenance cost

• Increased chance of misconfiguration

DUTS

• Software-oriented architecture with consistent register access

• Shared design philosophy across all timer functions

• Easier reuse across projects and platforms

Result: Reduced firmware complexity and faster development cycles.

5. Functional Breadth in a Single IP

Result: One IP Core replaces an entire timing subsystem.

6. Scalability Across Projects

Discrete timers

• Different IP mixes per product

• Harder to standardize designs

DUTS

• Same IP scales from minimal embedded systems to complex SoCs

• Interface width selectable (8-bit or 32-bit)

• Suitable for both FPGA prototyping and ASIC production

Result: A reusable timing platform across product families.

7. Verification and Long-Term Cost Reduction

Discrete timers

• Independent verification effort per IP

• Higher regression complexity

DUTS

• Single, well-verified subsystem

• Reduced verification scope and maintenance cost

• Lower total cost of ownership (TCO) over product lifetime

Result: Lower NRE and faster time to market.

Summary: When DUTS Makes the Most Sense

Choose DUTS if your design requires:

• Multiple timers, PWM, watchdog, and event handling

• Deterministic real-time behavior

• Minimal area and power consumption

• Clean software architecture and reuse

DUTS replaces a collection of discrete timers with a single, configurable, and synthesis-optimized timing subsystem—engineered for modern FPGA and ASIC designs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• PWM:
  • Up to Four 8-bit pulse widths or concatenated two 16-bits modulated waveforms
  • Three software-selectable clock sources
  • Software selectable polarity of the output waveform
  • Double buffered period and duty cycle registers for each PWM channel
• Timer 1:
  • Free running 16-bit counter with a 4-stage programmable prescaler
  • Timer overflow function
  • Up to four independent, configurable Input Capture functions
  • Up to five Output Compare, configurable functions
  • Interrupt controls and separate interrupt vectors of each IC, OC, and timer overflow
• Timer 2:
  • 16-bit counter with a 4-stage programmable prescaler
  • Up to four Output Compare functions
  • One Input Capture function
  • Event counting mode
  • Possibility to stop the counter
  • Timer overflow function
  • Interrupt controls and interrupt vectors of IC, OC, and timer overflow
• Timer 3:
  • 16-bit counter with a 3-stage programmable prescaler or with Timer 1 clock rate
  • Up to four Output Compare functions
  • One Input Capture function
  • Event counting mode
  • Possibility to stop the counter
  • Timer overflow function
  • Interrupt controls and interrupt vectors of IC/OC and timer overflow
• Real-Time Interrupt:
  • Hardware interrupts at a fixed periodic rate
  • Four different interrupt rates
  • Constant RTI timeouts
• Computer Operates Properly:
  • Configurable clock source
  • Scaling of watchdog overflow time
  • Protection from software malfunctions
• Pulse Accumulator:
  • 8-bit counter
  • Event counter mode and gated time accumulation mode
  • Maskable interrupts
• Fully synthesizable
• No internal tri-states
• Available system interface wrappers:
  • Native 8-bit interface
  • Native 32-bit interface
  • AMBA – APB / AHB / AXI Lite Bus
• Configurable reset
• Configurable interface control pins activity level
• Simple internal structure configuration