D68000-BDM

The D68000-BDM soft core is a high-performance, 32-bit microprocessor IP Core, fully binary-compatible with the industry-standard 68000, including upward compatibility with MC68008, MC68010, and MC68020 architectures. Featuring a 16-bit data bus and 24-bit address bus, this core executes programs with improved efficiency compared to the classic 68000.

Our core is delivered with a fully automated test bench and a complete set of verification tests, ensuring smooth SoC integration and validation at every stage of the design flow.

To demonstrate real-world functionality, the D68000-BDM has been successfully integrated with the uCLinux operating system. A dedicated testing platform was built using the CYCLONE-II DoCD2_C2_ETH_SDRAM32 FPGA board with onboard memory and peripherals, showcasing the core’s full compatibility and robustness. This setup enables a flexible, ready-to-use platform with the D68000-BDM as the main processor, leveraging existing GPL-based software and tools from the uCLinux ecosystem.

Designed as a technology-independent solution, the D68000-BDM IP Core is suitable for FPGA and ASIC implementations, industrial legacy systems, and embedded SoC applications requiring reliable, high-performance 68000-class processing.

Key Features:

• Binary-compatible with MC68008, MC68010, and MC68020

• 16-bit data bus, 24-bit address bus

• Enhanced instruction set for improved execution speed

• Fully automated test bench and validation suite

• Proven integration with uCLinux on FPGA

• Flexible platform for embedded and SoC designs

• Technology-independent – compatible with multiple FPGA & ASIC vendors

We have used the worldwide known Operating System for embedded solutions – uCLinux, to run with the D68000. Such a combination of hardware and software creates a very useful and flexible platform with the D68000 IP Core as the main processor. Most of the applications and tools were already available as GPL-based software. As a source for all information regarding uCLinux we have used http://www.uclinux.org/.

DCD-SEMI D68000 Family – IP Core Comparison Table

How to Choose

• Choose D68000 if you need a pure 68000 replacement with minimal bus width and maximum legacy fidelity.

• Choose D68000-CPU32 if your software targets CPU32 MCUs and needs higher performance with a 32-bit bus.

• Choose D68000-CPU32+ if you want the fastest 68k-compatible core, extended instruction set, and built-in debug for modern FPGA/ASIC designs.

Watch the D68000-BDM presentation on DCD’s You Tube:

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with 68000 industry standard
• MULS, MULU take 28 clock periods
• DIVS, DIVU take 28 clock periods
• Optimized shifts and rotations
• Idle cycles removed to improve performance
• Shorter effective address calculation time
• Bus cycle timings identical to 68000
• 32 bit data and address registers
• 14 addressing modes:
  • Direct:
    • Data register direct
    • Address register direct
  • Indirect:
    • Register indirect
    • Postincrement register indirect
    • Predecrement register indirect
    • Register indirect with offset
    • Indexed register indirect with offset
  • PC relative:
    • Relative with offset
    • Relative with index and offset
  • Absolute data:
    • Absolute short
    • Absolute long
  • Immediate data:
    • Immediate
    • Quick immediate
    • Implied
• 5 data types supported:
  • bits
  • BCD
  • bytes, words and long words
• Arithmetic Logic Unit includes:
  • 8,16,32-bit arithmetic & logical operations
  • 16×16 bit signed and unsigned multiplication
  • 32/16 bit signed and unsigned division
  • Boolean operations
• Interrupt controller:
  • 7 priority levels interrupt controller
  • Unlimited number of virtual interrupt sources
  • Vectored and auto-vectored modes
• Memory interface includes:
  • Up to 4 GB of address space
  • 16-bit data bus
  • Asynchronous bus control
• M6800 family synchronous interface
  • 3- and 2- wire bus arbitration
  • Supervisor and user modes
• Fully synthesizable
• Static synchronous design
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available