D68000-BDM

The D68000-BDM soft core is binary-compatible with an industry-standard 68000 32-bit microprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, the code is compatible with MC68008, upward compatible with MC68010 virtual extensions, and MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instruction set, which allows the execution of the program with higher performance than a standard 68000 core. The D68000-BDM s delivered with a fully automated test bench and complete set of tests, allowing easy package validation at each stage of the SoC design flow. A special testing platform has been built to run D68000-BDM with uCLinux Operating System. The main goal of using uCLinux was to show that the D68000 microprocessor IP Core is fully functional and well validated. For that purpose, we have built a complete testing system based on CYCLONE-II DoCD2_C2_ETH_SDRAM32 FPGA board, with some onboard memories and peripherals. We have used the worldwide known Operating System for embedded solutions – uCLinux, to run with the D68000. Such a combination of hardware and software creates a very useful and flexible platform with the D68000 IP Core as the main processor. Most of the applications and tools were already available as GPL-based software. As a source for all information regarding uCLinux we have used http://www.uclinux.org/.

Watch the D68000-BDM presentation on DCD’s You Tube:

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with 68000 industry standard
• MULS, MULU take 28 clock periods
• DIVS, DIVU take 28 clock periods
• Optimized shifts and rotations
• Idle cycles removed to improve performance
• Shorter effective address calculation time
• Bus cycle timings identical to 68000
• 32 bit data and address registers
• 14 addressing modes:
  • Direct:
    • Data register direct
    • Address register direct
  • Indirect:
    • Register indirect
    • Postincrement register indirect
    • Predecrement register indirect
    • Register indirect with offset
    • Indexed register indirect with offset
  • PC relative:
    • Relative with offset
    • Relative with index and offset
  • Absolute data:
    • Absolute short
    • Absolute long
  • Immediate data:
    • Immediate
    • Quick immediate
    • Implied
• 5 data types supported:
  • bits
  • BCD
  • bytes, words and long words
• Arithmetic Logic Unit includes:
  • 8,16,32-bit arithmetic & logical operations
  • 16×16 bit signed and unsigned multiplication
  • 32/16 bit signed and unsigned division
  • Boolean operations
• Interrupt controller:
  • 7 priority levels interrupt controller
  • Unlimited number of virtual interrupt sources
  • Vectored and auto-vectored modes
• Memory interface includes:
  • Up to 4 GB of address space
  • 16-bit data bus
  • Asynchronous bus control
• M6800 family synchronous interface
  • 3- and 2- wire bus arbitration
  • Supervisor and user modes
• Fully synthesizable
• Static synchronous design
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available