DQ80251

The DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable – this allows an easy selection of features and peripherals, in order to create a dedicated system. It was designed with a special concern about the performance to power consumption ratio. This ratio is extended by an advanced power management unit – the PMU. The DQ80251 utilizes 20 years of DCD’s know-how with triumphant 8051 architectures. The core is 100% binary-compatible with industry-standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251:

• BINARY (where the original 80C51 compiled code is executed), and
• SOURCE (a native 80C251 mode using all DQ80251 performance).

The DQ80251 has a built-in, configurable DoCD-JTAG on-chip debugger, supporting Keil DK251 and a standalone DoCD debug software. Dhrystone 2.1 benchmark program runs over 75 times faster than the original 80C51 and 6 times faster than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low-power applications, where the core can be clocked over fifty times slower than the original implementation, with no performance penalty. Additionally, the compiled code size for the SOURCE mode is about 2 times smaller compared to the identical standard 8051 code, due to the higher efficiency of DQ80251 instructions. The DQ80251 is delivered with fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each of our 80251 cores has built-in support for DCD’s Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of running applications. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals.

Watch the DQ80251 presentation on DCD’s YouTube:

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• 100% binary compatible with industry standard 80C251, implementing BINARY and SOURCE modes
• Single clock period per most of instructions
• Quad-Pipelined architecture enables to run 75 times faster than the original 80C51 and 6 times faster, than the 80C251 at the same frequency
• Up to 75.08 VAX MIPS ratio
• Up to 8M bytes of Program Memory
• Up to 32k bytes of internal (on-chip) Data Memory
• Up to 8M bytes of external (off-chip) Data Memory
• Up to 16 MB of total memory space for CODE and DATA
• 32k bytes of extended stack space
• User programmable Program Memory Wait States solution – for wide range of memories’ speed
• User programmable Extended Data Memory Wait States solution – for wide range of memories’ speed
• De-multiplexed Address/Data bus, to allow easy connection to memory
• Full Program Memory writes
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• No internal tri-states
• Scan test ready
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available