DAES XTS - cryptographic co-processor for lightweight cryptography

Description

DAES XTS IP Core from Digital Core Design is a compact cryptographic co-processor designed to seamlessly implement the Rijndael encryption algorithm in compliance with FIPS 197 Advanced Encryption Standard, specifically in XTS mode (by IEEE Std 1619-2007 standards).

Tailored for IoT and embedded devices applications requiring robust hardware disk encryption, this solution excels with its support for encrypted memories such as FLASH or RAM, thanks to the random data access block function.

The DAES XTS is an ideal choice for security-conscious environments, ranging from IoT devices to cloud servers, owing to the widespread adoption of the AES block cipher. Its hardware-based implementation offers substantial advantages in both security and performance compared to software-based alternatives. It is important to note that Ciphertext-Stealing mode is currently not supported; therefore, the DAES XTS expects memory sectors to be aligned to multiples of 128-bit blocks.

Furthermore, seamless integration is possible with a diverse array of SPI memory controllers, enhancing the versatility and compatibility of the DAES XTS for a wide range of applications. Elevate your security measures with this lightweight yet powerful cryptographic solution.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

Key features

  • Support AES‐XTSmode—IEEE Std 1619‐2007 standard compliance
  • Support 128 and 256‐bit key size
  • Random memory block access support
  • Internal key expansion module
  • Minimal resource usage for embedded systems
  • Optional embedded memory interface ready wrapper

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