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DCAN XL

Description

DCAN XL IP Core — Next-Generation CAN XL Controller Bridging CAN FD and 100 Mbit Ethernet

The DCAN XL IP Core from DCD-SEMI represents a major leap forward in in-vehicle communication, bridging the gap between CAN FD and 100 Mbit Ethernet. Designed for high-bandwidth, next-generation automotive architectures, it supports data rates up to 20 Mbit/s and payloads up to 2048 bytes, enabling dramatically faster and more flexible data transmission than previous CAN standards.

65kBWith support for higher-layer protocols, Ethernet frame tunneling, and extended data fields, the DCAN XL IP Core delivers the scalability required for emerging automotive, industrial, and smart mobility applications.

Backward-Compatible with CAN, CAN FD, and CAN XL

While offering advanced capabilities, the DCAN XL IP Core retains the proven benefits of the CAN ecosystem. It provides full backward compatibility with:

  • Classical CAN

  • CAN FD

  • CAN XL

Physical connection to the CAN bus requires external transceivers, with:

  • Standard CAN transceivers recommended below 10 Mbit/s

  • CAN SIC XL transceivers required above 10 Mbit/s

This ensures reliable communication tailored to system requirements.

Optimized Architecture for High-Speed Message Handling

The DCAN XL IP Core utilizes an external single- or dual-ported Message RAM, connected through a Generic Master Interface for optimal throughput. This design enables:

  • High-speed message processing

  • Reduced CPU load

  • Scalable RAM configuration

  • Flexible system integration

The host CPU connects through a 32-bit Generic Interface, compatible with widely used SoC/FPGA bus wrappers such as:

  • AMBA

  • Intel/Altera Avalon Bus

  • Xilinx OPB Bus

Available in Basic and Safety-Enhanced (ISO 26262 SEooC) Versions

The DCAN XL IP Core is offered in:

  • Basic Version

  • Safety-Enhanced Version, designed as an ISO 26262-10 Safety Element out of Context (SEooC)

The Safety-Enhanced variant provides:

  • Complete ISO 26262 safety documentation

  • Fully validated FMEDA analysis

  • Optional integrated safety mechanisms

  • Third-party audited work products

ASIL-B Ready Functional Safety — Extensible Toward ASIL-D

The completed safety analysis confirms that the DCAN FD FULL IP Core meets all ASIL-B functional safety requirements, achieving the following key metrics:

  • SPFM > 90% (Single Point Fault Metric)

  • LFM > 60% (Latent Fault Metric)

These results validate the suitability of the DCAN FD FULL for integration into automotive systems targeting ASIL-B safety goals.
Additionally, DCD-SEMI can provide enhanced variants tailored to support architectures requiring higher safety integrity levels — including ASIL-D — to meet specific OEM or Tier-1 requirements.

Why Engineers Choose DCAN XL

  • Supports CAN, CAN FD, and CAN XL

  • Up to 20 Mbit/s and 2048-byte payloads

  • Ethernet tunneling & higher-layer protocol support

  • CPU-friendly architecture

  • ASIC/SoC/FPGA-ready design

  • Developed in line with ISO26262 as SEooC.

  • ASIL-B & ASIL-D compliant.

  • Delivered with functional safety-related documentation.

  • Independent third-party audit assessment.

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For additional technical details or optional features, contact info@dcd-semi.com

Download full specification

DCAN XL ASIC
DCAN XL INTEL FPGA
DCAN XL LATTICE
DCAN XL MICROSEMI
DCAN XL XILINX

Key features

  • Designed in accordance with ISO 11898‐1:2024 specification and CiA610-1 specification
  • Supports CAN, CAN FD and CAN-XL frames
  • Supports up to 64 bytes CAN FD frame and up to 2048 bytes CAN-XL data frame
  • Flexible data rates supported
  • AUTOSAR support
  • SAE J1939 support
  • 32‐bit CPU slave interface
  • Data rate up to 1Mbps in Classic CAN mode,  up to 8Mbps in FD mode, up to 20Mbps in XL mode
  • Optional PWM coding allows bit-rates of 10 Mbit/s and more depending on the physical network design
  • Up to 128 Base ID filters
  • Up to 64 Extended ID filters
  • 2 Configurable receive FIFO
  • Overload frame is generated on FIFO overflow
  • Up to 32 dedicated Transmit Buffers
  • Configurable Transit Buffers to FIFO or QUEUE
  • Configurable Transmit Event FIFO
  • Normal and Listen Only modes supported
  • Transmitter Delay Compensation up to six data bits long
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Timestamp according to CiA 603 support
  • Two configurable interrupt lines
  • Two clock domains (CAN clock and CPU clock)
  • Fully synthesizable
  • Static synchronous design with positive edge clocking and synchronous reset
  • No internal tri‐states
  • Scan test ready
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Lite Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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