Description

The CAN XL IP presents a revolutionary advancement bridging the gap between CAN FD and 100Mbit Ethernet, making strides in data transmission technology. With support for data rates reaching up to 20 Mbit/s and accommodating data fields up to 2048 bytes in length, it surpasses previous standards. Moreover, it offers the flexibility of employing higher layer protocols and Ethernet frame tunneling, enhancing its versatility in various applications.

Retaining the reliability and advantages of the CAN protocol, this solution ensures seamless integration while catering to evolving technological needs. Backward compatibility with Classical CAN, CAN FD, and CAN XL further solidifies its adaptability. For physical connectivity to the CAN bus, external transceiver hardware is essential, with CAN transceivers for bitrates below 10Mbps and CAN SIC XL transceivers for bitrates exceeding 10Mbps.

Notably, the CAN XL implementation from DCD incorporates a single or dual-ported Message RAM located externally, facilitating efficient message handling through the Generic Master Interface. Integration with the host CPU is effortless through the 32-bit Generic Interface, compatible with popular interface wrappers such as AMBA, Altera Avalon Bus, and Xilinx OPB Bus.

This advanced solution is available in two versions, Basic and Safety-Enhanced, with the latter developed as an ISO26262-10 Safety Element out of Context. It can be further enhanced with necessary safety mechanisms, accompanied by comprehensive safety documentation meeting ISO26262 standards. Third-party audits validate the safety-related work products, ensuring compliance with Automotive Safety Integrity Level ASIL-B requirements.

The thorough FMEDA analysis provided by DCD offers step-by-step instructions for seamless integration and system-level safety analysis. Achieving ASIL-B readiness, this design is suitable for integration into Automotive Safety Systems, with the option for higher ASIL level readiness. For additional details and optional features, customers are encouraged to reach out to DCD support.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

Key features

  • Designed in accordance with ISO 11898‐1:2024 specification (tbc) and CiA610-1 specification
  • Supports CAN, CAN FD and CAN-XL frames
  • Supports up to 64 bytes CAN FD frame and up to 2048 bytes CAN-XL data frame
  • Flexible data rates supported
  • AUTOSAR support
  • SAE J1939 support
  • Simple 8/16/32‐bit CPU slave interface
  • Data rate up to 1Mbps in Classic CAN mode,  up to 8Mbps in FD mode, up to 20Mbps in XL mode
  • Optional PWM coding allows bit-rates of 10 Mbit/s and more depending on the physical network design
  • Up to 128 Base ID filters
  • Up to 64 Extended ID filters
  • 2 Configurable receive FIFO
  • Overload frame is generated on FIFO overflow
  • Up to 32 dedicated Transmit Buffers
  • Configurable Transit Buffers to FIFO or QUEUE
  • Configurable Transmit Event FIFO
  • Normal and Listen Only modes supported
  • Transmitter Delay Compensation up to six data bits long
  • Ability to abort transmission
  • Readable error counters
  • Last Error Code
  • Timestamp according to CiA 603 support
  • Two configurable interrupt lines
  • Two clock domains (CAN clock and CPU clock)
  • Fully synthesizable
  • Static synchronous design with positive edge clocking and synchronous reset
  • No internal tri‐states
  • Scan test ready
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Lite Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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