DeSPI Controller IP

DESPI eSPI Controller IP Core – High-Speed, Fully Configurable eSPI Controller for FPGA and ASIC

The DESPI eSPI Controller IP Core is a fully configurable Enhanced Serial Peripheral Interface (eSPI) Controller, compliant with the eSPI Base Specification Revision 1.6. It is designed for high-performance embedded systems, enabling reliable, low-latency communication between host processors, microcontrollers, and eSPI-enabled peripheral devices, including Embedded Controllers (EC) in Intel-based platforms.

As a modern replacement for the legacy LPC (Low Pin Count) interface, the DESPI Controller IP delivers high-speed serial communication with support for single, dual, and quad SPI modes. With serial clock frequencies up to 66 MHz, it ensures efficient data transfer, reduced pin count, and improved system throughput in advanced SoC designs.

Its modular and scalable architecture allows seamless integration into FPGA and ASIC environments, making it suitable for a wide range of applications requiring robust eSPI host/controller functionality.

Key Features

• eSPI Controller IP compliant with eSPI Base Specification Rev. 1.6

• Configurable Controller mode for integration into complex SoC architectures (looking for an eSPI Target? here it is)

• High-speed SPI interface up to 66 MHz for low-latency communication

• Support for Single, Dual, and Quad SPI transfers to maximize bandwidth and performance

• Large, highly configurable shared memory buffer enables efficient and flexible frame and data storage to fit any needs.

• Customizable peripheral channels, including memory-mapped I/O, Virtual Wire signals, and event signaling

• Technology-agnostic RTL design compatible with all major FPGA and ASIC vendors

• Optimized for Intel-based systems and embedded controller communication

Typical Applications

• Host interface for Embedded Controllers (EC) in Intel CPU platforms

• FPGA and ASIC-based SoC designs requiring eSPI Master functionality

• High-speed data acquisition systems and industrial embedded platforms

• Multi-slave microcontroller systems with low-latency communication requirements

• Replacement of legacy LPC interfaces in modern hardware architectures

The DESPI eSPI Controller IP Core is fully customizable to meet specific system and integration requirements, making it a reliable solution for next-generation embedded systems, microcontrollers, and high-performance digital designs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.