DQSPI

DQSPI – High-Performance Quad SPI IP Core for APB, AHB, and AXI Designs

The DQSPI is a revolutionary Quad SPI IP Core engineered for design teams who demand maximum throughput, low latency, and flexible integration. Fully compatible with APB, AHB, and AXI buses, it delivers one of the fastest serial memory interfaces available for both SoC and FPGA designs.

Supporting Single, Dual, and Quad SPI modes with Double Data Rate (DDR) operation, the DQSPI enables 8 bits of data per SCK cycle, making it ideal for systems requiring high-speed code execution, fast memory access, or real-time data streaming.

Engineered for Modern Embedded Systems

The DQSPI interfaces seamlessly with all 8-, 16-, and 32-bit processors, regardless of endianness. Its flexible architecture supports standard SPI peripherals from multiple vendors, which makes it an excellent choice for new designs and drop-in replacements.

Typical use cases include:

• high-speed Quad SPI flash memories

• real-time data logging

• inter-processor communication

• Execute-In-Place (XiP) architectures

• low-pin-count, high-performance embedded systems

Key Performance Features

Blazing-Fast Transfers

• Supports Single, Dual, and Quad SPI

• DDR protocol doubles bandwidth

• Achieves data rates up to CLK/2 (vs. typical vendor limit of CLK/8)

• Ideal for high-performance SoCs and FPGAs

Advanced Clock Control

• Programmable clock polarity, phase, and four clocking protocols

• Supports a wide variety of synchronous serial peripherals

• Precisely tuned for embedded applications with tight timing budgets

Master/Slave Configurable

The DQSPI can operate as a master or slave, enabling seamless integration into:

• multi-master systems

• shared bus environments

• communication between processors or controllers

Robust Reliability and Error Handling

To support demanding applications, the DQSPI includes advanced safety and reliability mechanisms:

• Write-collision detection

• Multiple-master mode fault detection

• Automatic disable of drivers under conflict

• Error-reporting logic for inter-processor communication

These features make the DQSPI highly reliable in automotive, industrial, and mission-critical embedded environments.

DMA Support for Maximum Throughput

The IP Core supports two independent DMA modes:

• Single-transfer mode

• Multi-transfer mode

This allows high-performance DMA units to interleave transfers with CPU cycles or perform burst data transfers without processor overhead.

Technology-Independent Design

Like all DCD-SEMI solutions, the DQSPI is:

• fully synthesizable

• portable across semiconductor technologies

• ready for ASIC, SoC, and FPGA implementation

This ensures long-term product scalability and easy migration across multiple platforms.

Fully Customizable IP Core

The DQSPI is delivered in a configuration tailored to your design requirements:

• width of data paths

• clocking scheme

• DMA options

• master/slave configuration

• peripheral compatibility

Our team customizes the DQSPI to minimize your integration effort and accelerate time-to-market.

Why Design Engineers Choose DQSPI

✔ Ultra-fast Quad SPI + DDR performance
✔ Compatible with APB, AHB, and AXI bus structures
✔ Supports any 8/16/32-bit CPU architecture
✔ XiP-ready for instant code execution from external flash
✔ Superior data rate (CLK/2 vs typical CLK/8)
✔ Robust error detection and multi-master support
✔ Fully configurable and technology-independent

Watch the DQSPI presentation on DCD’s YouTube:

Which One to Choose DQSPI vs DOSPI

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• Operates with 8, 16 and 32 bit CPUs
• Full duplex synchronous serial data transfer
• DMA support
• Support for 32, 16 and 8 bit systems
• Support for various system Bus Standards
• Single, Dual and Quad SPI transfer
• DDR support (Double Data Rate)
• Multimaster system supported
• Optional FIFO size extension (128, 256, 512B)
• Up to 7 SPI slaves can be addressed (more Slave Select Outputs can be added upon request)
  • Software Slave Select Output – SSO ‐ selection
  • Automatic Slave Select outputs assertion during each byte transfer
• System error detection
• Interrupt generation
• Various Bit rates supported
• Bit rate in fast SPI Mode ½ CLK
• Four transfer formats
• Simple CPU and DMA interface
• Fully synthesizable, static synchronous de-sign with no internal tri‐states
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus