Enhanced Serial Peripheral Interface – Master/Slave with single, dual, and quad eSPI Bus support for Intel CPU’s
Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller
The DESPI is a fully configurable eSPI master/slave device supporting all features described in Enhanced Serial Peripheral Interface Base Specification rev. 1.0. The DESPI master is to be used by the microcontroller to communicate with eSPI peripheral devices. The DESPI slave is to be used as an eSPI peripheral device, e.g. an Embedded Controller attached to the Intel CPU system.
The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. It is a technology-independent design that can be implemented in a variety of process technologies. The DESPI is flexible enough to interface directly with numerous peripherals. The system might be configured as well as master as slave. Depending on the core configuration, the _in or _out lines are utilized. The serial clock may be up to 66MHz. The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration meeting users’ requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs able to store up to 4096+16 bytes (header and data payload or separate buffers for every eSPI channel and for posted/non-posted transfers), a customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines.
The controller is capable to operate in several eSPI configurations: Single Master- Single Slave, Single Master – Multiple Slaves.
All DCD’s IP Cores are technology independent which means that they are 100% compatible with all FPGA & ASIC vendors e.g.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI)
- Supports Master and Slave Modes
- Supports Single, Dual and Quad modes
- Supports TX and RX operation as per specs
- Support for
- Command Phase
- Turn-Around Phase
- Response Phase
- Baud Rate selection
- Slave Triggered Transactions
- Power management Event
- Interrupts and Alerts
- In-band reset
- Support for multiple channels
- Peripheral channel
- Virtual wire Channel
- OOB Message (Tunneled SMBus) Channel
- Run-time Flash Access Channel
- Various Master/Slave errors detection
- CRC Checking and generation
- The simple interface allows easy connection to microcontrollers
- Fully synthesizable, static synchronous design with no internal tri-states
DSPI bridge to APB, AHB, and AXI bus, it is a fully configurable SPI master/slave device, which allows you...
master & Multi-master operations
8 SPI slave select lines
system error detection
DQSPI bridge to APB, AHB, and AXI bus, it is a revolutionary quad SPI designed to offer the fastest operations...
the fastest available operations
for any serial SPI memory
supports all 8, 16, 32-bit CPUs