DHDLC

DHDLC IP Core – HDLC Protocol Controller with AXI, AHB, and APB Interfaces

The DHDLC IP Core from DCD-SEMI is a high-performance HDLC protocol controller designed for seamless integration into FPGA and ASIC designs. Acting as a flexible HDLC bridge to APB, AHB, and AXI bus architectures, DHDLC enables reliable implementation of one of the most widely used serial communication protocols in embedded and networking systems.

The core fully offloads HDLC frame handling from the CPU, including bit stuffing and unstuffing, address field insertion and detection, and frame integrity verification using CRC16 and CRC32. This significantly reduces processor load while increasing overall system throughput and determinism.

Key Features for FPGA and ASIC Designs

• Complete HDLC protocol support with transmit and receive paths

• CRC16 and CRC32 generation and checking

• Independent TX and RX FIFO buffers to maximize data throughput

• Maskable interrupt system and DMA request support for low-latency data handling

• Optional Frame Status Buffer reporting frame length and error conditions

• Configurable FIFO depths for optimal resource utilization

• Synthesis-time feature trimming to reduce area and power consumption

Scalable Bus Interfaces

The DHDLC IP Core is fully scalable and tailored to project-specific requirements, making it suitable for both deeply embedded systems and high-end SoCs. Supported host interfaces include:

• Compact 8-bit SRAM-like interface

• 32-bit AXI4 slave interface with burst support

• AXI4-Lite interface

• AHB and APB slave interfaces

This flexibility allows easy integration into modern SoC architectures and legacy designs alike.

Optimized for System Performance

By combining hardware-based protocol processing with FIFO buffering, DMA support, and interrupt handling, the DHDLC IP Core ensures high data throughput, predictable latency, and minimal CPU intervention—critical requirements for real-time and communication-intensive applications.

Target Applications

The DHDLC IP Core is an ideal building block for implementing higher-level protocols and communication stacks, including:

• PPP (Point-to-Point Protocol)

• X.25

• V.42

• LAP-B

• SDLC

• ISDN

• and many other HDLC-based protocols

Why Choose DCD-SEMI DHDLC IP Core?

• Proven FPGA- and ASIC-ready IP

• Highly configurable and scalable architecture

• Reduced integration effort and faster time-to-market

• Optimized for performance, area efficiency, and power

The DHDLC IP Core delivers a robust, configurable, and production-ready HDLC solution for engineers designing modern communication-enabled systems.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Two separate receiver and transmitter interfaces.
• Two separate, configurable FIFO buffers for receiver and transmitter
• Bit stuffing and unstuffing
• Address recognition for receiver and address insertion for transmitter
• Two or one byte address field
• CRC-16 and CRC-32 computation and checking
• Collision detection
• Byte alignment error detection
• Programmable number of bits for idle detection
• NRZI coding support
• Shared flags, shared zeroes support
• Pad fill with flags option
• Transmitter clock generation
• 8-bit, 16-bit, 32-bit CPU interface
• Interrupt output for handling control flags and FIFOs’ filling
• Configurable core parameters
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus