DHDLC

DHDLC bridge to APB, AHB, and AXI bus, provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload are a must-be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt, and DMA interface requests. The DHDLC is a fully scalable IP Core, which makes it a perfect solution for both high-end and deeply embedded projects. It’s tailored to your project needs and can be provided with:

• small 8-bit SRAM-like interface
• 32-bit full AXI4 slave interface with burst support
• AXI4Lite interface
• AHB and APB slave interfaces

The optional Frame Status Buffer stores information about frame size and error conditions. Moreover, the size of the receiver and transmitter FIFO buffers is configurable. You can also easily remove unused features before the synthesis process. All that and much more make the DHDLC an ideal solution for very popular higher-level protocol implementations like e.g. PPP (Point-to-Point), X.25, V.42, LAB-B, SDLC, ISDN, and many others.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Two separate receiver and transmitter interfaces.
• Two separate, configurable FIFO buffers for receiver and transmitter
• Bit stuffing and unstuffing
• Address recognition for receiver and address insertion for transmitter
• Two or one byte address field
• CRC-16 and CRC-32 computation and checking
• Collision detection
• Byte alignment error detection
• Programmable number of bits for idle detection
• NRZI coding support
• Shared flags, shared zeroes support
• Pad fill with flags option
• Transmitter clock generation
• 8-bit, 16-bit, 32-bit CPU interface
• Interrupt output for handling control flags and FIFOs’ filling
• Configurable core parameters
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus