D8530

D8530 IP Core – Dual-Channel USART Controller for FPGA & ASIC

The D8530 IP Core from DCD-SEMI is a highly versatile dual-channel USART (Universal Synchronous/Asynchronous Receiver/Transmitter) designed for seamless integration into FPGA and ASIC designs. Acting as a configurable bridge to APB, AHB, and AXI bus architectures, the D8530 enables reliable serial communication across a wide range of embedded, industrial, and telecommunications systems.

Designed for use with 8-bit and 16-bit microprocessors, the D8530 operates as a serial-to-parallel and parallel-to-serial controller, offering exceptional flexibility through software configurability. Integrated on-chip baud rate generators allow precise timing control without external components, reducing system complexity.

Comprehensive Serial Protocol Support

The D8530 IP Core supports virtually all serial communication formats, including:

• Asynchronous UART modes

• Synchronous byte-oriented protocols (e.g. IBM® Bisync)

• Synchronous bit-oriented protocols, such as HDLC and IBM SDLC

In synchronous modes, the core can generate and check CRC codes, enabling robust data integrity verification across multiple protocol variants.

Advanced Configuration and Control

Each channel of the D8530 is controlled via a rich register set, consisting of 14 write registers and 7 read registers per channel (depending on configuration). Within each operating mode, the core supports extensive protocol customization, including:

• Odd or even parity checking

• Variable data sizes, stop bits, and framing formats

• Character insertion and deletion

• Break and abort generation and detection

• Programmable CRC generation and checking

This level of configurability makes the D8530 suitable for both legacy communication standards and modern embedded designs.

Modem Control and GPIO Flexibility

The D8530 provides full modem control on both channels, enabling seamless integration with traditional communication hardware. In applications where modem signaling is not required, these signals can be repurposed as general-purpose I/O, further increasing design flexibility.

Scalable Bus Interfaces

To fit a wide range of SoC architectures, the D8530 IP Core can be delivered with:

• AXI4 or AXI4-Lite slave interface

• AHB slave interface

• APB slave interface

This scalability makes the D8530 an ideal solution for both deeply embedded systems and high-performance FPGA-based platforms.

Typical Applications

• Telecommunications equipment

• Industrial controllers

• LAN and networking devices

• Legacy protocol bridging

• FPGA-based SoCs requiring flexible serial interfaces

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with Z85C30
• Dual Channel: A, B
• Configuration capability
• Asynchronous mode:
  • Asynchronous (x16, x32, or x64 clock
  • Isochronous (x1 clock)
• Character-Oriented mode:
  • Monosynchronous
  • Bisynchronous
  • External Synchronous
• Bit-Oriented mode:
  • SDLC/HDLC
  • SDLC/HDLC Loop
• Complete status reporting capabilities
• Receiver data FIFO and Error FIFO
• SDLC Frame FIFO
• Data encoder\decoder:
  • NRZ, NRZI
  • FM0, FM1
  • Manchester (require external logic)
• Line break generation and detection
• Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Auto Echo
  • Break, parity, overrun, framing error simulation
• Fully synchronous design with no internal tristate buffers
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus