DI2CMS

DI2CMS bridge to APB, AHB, and AXI bus, it is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short-distance data transmission between many devices. The DI2CMS core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:

• a master or
• slave transmitter/receiver

depending on a working mode determined by the microprocessor/microcontroller. The DI2CMS core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and a high-speed transmission mode (the DI2CMS supports all transmission speed modes). The built-in timer allows operation from a wide range of clk frequencies. The DI2CMS is technology independent, so either VHDL or VERILOG design can be implemented in a variety of process technologies. Furthermore, it can be also completely customized in accordance with your needs. The DI2CMS is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• Conforms to v.3.0 of the I2C specification
• Master mode
  • Master operation
    • Master transmitter
    • Master receiver
  • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Arbitration and clock synchronization
  • Support for multi-master systems
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Build-in 8-bit timer for data transfers speed adjusting
• Slave mode
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • User-defined data setup time
• User-defined timing (data setup, start setup, start hold, etc.)
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Interrupt generation
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready