DI2CMS

DI2CMS IP Core – I2C, SMBus & PMBus Controller for FPGA & ASIC

The DI2CMS IP Core from DCD-SEMI is a flexible and robust I2C bus controller designed to seamlessly bridge microprocessors and SoC architectures with I2C, SMBus, and PMBus interfaces. Fully compliant with the I2C v3.0 specification, DI2CMS enables reliable serial communication in modern FPGA and ASIC designs.

The core consists of two tightly integrated modules: DI2CM (I2C Master) and DI2CS (I2C Slave), allowing the IP Core to operate as either a master or slave device on the bus. This dual-mode capability makes DI2CMS suitable for a wide range of embedded, industrial, and power-management applications.

Advanced I2C Features for Complex Systems

DI2CMS supports advanced I2C capabilities required in sophisticated multi-device environments, including:

• Multi-master arbitration

• Clock synchronization

• Controller clock stretching

• Full support for SMBus and PMBus protocols

These features ensure reliable operation in multi-master systems and enable seamless interoperability with a broad ecosystem of I2C-compatible devices.

Full-Speed I2C, SMBus and PMBus Operation

The DI2CMS IP Core supports configurable transmission speeds up to 3.4 Mb/s, covering all standard and extended I2C operating modes:

• Normal mode – 100 kHz

• Fast mode – 400 kHz

• Fast-plus mode – 1 MHz

• High-Speed mode – 3.4 MHz

In addition, the core supports all predefined SMBus and PMBus clock frequencies, making it ideal for system monitoring, power management, and control applications.

SoC-Friendly Integration and Scalability

Designed with technology independence in mind, DI2CMS integrates easily into a wide range of SoC architectures. Supported CPU interfaces include:

• AMBA APB

• AMBA AHB

• AMBA AXI

The IP Core is suitable for implementation across multiple FPGA and ASIC process technologies and can be fully customized to meet application-specific requirements, optimizing area, performance, and power consumption.

Verified and Production-Ready IP

To ensure smooth integration into the SoC design flow, the DI2CMS IP Core is delivered with:

• Automated testbench

• Comprehensive verification test suite

• Proven compliance with I2C v3.0, SMBus, and PMBus standards

This validation infrastructure accelerates design verification and reduces integration risk.

Typical Applications

• Power management and voltage regulation (PMBus)

• System monitoring and control (SMBus)

• Embedded controllers and SoCs

• Industrial and automotive electronics

• FPGA-based platforms requiring I2C connectivity

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Conforms to the I2C v3.0 specification
• Support for SMBus and PMBus protocols
• Both master and slave transmitter/receiver modes
• Multi-master support with bus arbitration
• Controller clock stretching and synchronization
• Clock stretching warning signal
• Clock low timeout detection
• User-configurable clock and data timings via:
  • Sythesis parameters
  • Dynamic registers reconfiguration
• 7 and 10-bit addressing in master mode
• SMBus Alert and PMBus control line support
• Up to 8 target addresses in slave mode
• Dynamic ACK bit control based on received data
• FIFO support in slave mode
• DMA support
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready