DI2CS

DI2CS IP Core – I2C Slave Controller for FPGA & ASIC

The DI2CS IP Core from DCD-SEMI is a flexible and standards-compliant I2C slave controller designed to provide a reliable interface between a microprocessor or microcontroller and an I2C bus in modern FPGA and ASIC designs. Delivered as a scalable bridge to APB, AHB, and AXI bus architectures, DI2CS enables seamless integration into a wide range of embedded and SoC platforms.

The core operates exclusively in slave mode, functioning as either a slave transmitter or slave receiver, with the operating role dynamically determined by the I2C master device on the bus.

Full Compliance with the Latest I2C Specification

DI2CS incorporates all features required by the latest I2C specification, ensuring reliable communication and interoperability with standard-compliant masters. Supported features include:

• Clock synchronization

• Arbitration

• High-speed transmission mode

These capabilities allow the core to operate correctly in both simple and complex I2C system topologies.

Support for All I2C Speed Modes

The DI2CS IP Core supports all standardized I2C transmission speeds, making it suitable for a broad range of performance requirements:

• Standard mode – up to 100 kb/s

• Fast mode – up to 400 kb/s

• Fast Plus mode – up to 1 Mb/s

• High-Speed mode – up to 3.4 Mb/s

This ensures compatibility with legacy peripherals as well as high-performance I2C systems.

SoC-Friendly and Technology Independent

Designed as a technology-independent IP Core, DI2CS can be implemented across multiple FPGA families and ASIC process technologies. To support modern SoC architectures, the core can be delivered with:

• AMBA APB interface

• AMBA AHB interface

• AMBA AXI interface

This flexibility allows DI2CS to be easily integrated into both deeply embedded designs and high-end SoC platforms.

Typical Applications

• I2C peripheral and device emulation

• Sensor and actuator interfaces

• System monitoring and control

• Industrial and consumer electronics

• FPGA-based SoCs requiring I2C slave functionality

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• Conforms to v.3.0 of the I2C specification
• Slave operation
  • Slave transmitter
  • Slave receiver
• Supports 3 transmission speed modes
  • Standard (up to 100 kb/s)
  • Fast (up to 400 kb/s)
  • Fast Plus (up to 1 Mb/s)
  • High Speed (up to 3,4 Mb/s)
• Double buffering of RX/TX data
• Configurable RX and TX FIFOs up to 256 bytes each
• Configurable length of SCL, SDA lines glitch filtering
• Allows operation from a wide range of input clock frequencies
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Interrupt generation
• User-defined data setup time
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready