DI2CS
Slave I2C bus controller with FIFO
Description
DI2CS bridge to APB, AHB, AXI bus, provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:
- a slave transmitter or
- slave receiver
depending on a working mode determined by the master device. The DI2CS core incorporates all features required by the latest I2C specification, including:
- clock synchronization,
- arbitration,
- high-speed transmission mode.
The DI2CS supports all transmission speed modes:
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
DCD’s IP Core is a technology-independent design and can be implemented in various process technologies.
DESIGN FEATURES:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Lattice,
- Microsemi / Microchip,
and others. - TSMC
- UMC
- SK Hynix
and others.
Key features
- Conforms to v.3.0 of the I2C specification
- Slave operation
- Slave transmitter
- Slave receiver
- Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Double buffering of RX/TX data
- Configurable RX and TX FIFOs up to 256 bytes each
- Configurable length of SCL, SDA lines glitch filtering
- Allows operation from a wide range of input clock frequencies
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Interrupt generation
- User-defined data setup time
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
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