I2C Bus Interface – Master
DI2CM bridge to APB, AHB, AXI bus, the core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:
- a master transmitter or
- master receiver
depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. The built-in timer allows operation from a wide range of clk frequencies. The DI2CM is a technology-independent design that can be implemented in a variety of process technologies.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Conforms to v.3.0 of the I2C specification
- Master operation
- Master transmitter
- Master receiver
- Support for all transmission speeds
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Arbitration and clock synchronization
- Support for multi-master systems
- Support for both 7-bit and 10-bit addressing formats on the I2C bus
- Interrupt generation
- Build-in 8-bit timer for data transfers speed adjusting
- Host side interface dedicated for microprocessors/microcontrollers
- User-defined timing (data setup, start setup, start hold, etc.)
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
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