DI2CM

DI2CM IP Core – I2C Master Controller for FPGA & ASIC

The DI2CM IP Core from DCD-SEMI is a robust and configurable I2C master controller designed to provide a seamless interface between a microprocessor or microcontroller and an I2C bus in modern FPGA and ASIC designs. Delivered as a flexible bridge to APB, AHB, and AXI bus architectures, DI2CM enables reliable I2C communication in embedded, industrial, and system-control applications.

The core operates exclusively in master mode, functioning as either a master transmitter or a master receiver, with the operating mode fully controlled by software running on the host processor.

Full Compliance with the Latest I2C Specification

DI2CM incorporates all essential features defined in the latest I2C specification, ensuring compatibility with a wide range of I2C-compliant peripherals and systems. Supported features include:

• Multi-master arbitration

• Clock synchronization

• High-speed transmission mode

• Reliable operation in complex multi-master environments

These capabilities make DI2CM suitable for both simple point-to-point designs and advanced multi-device I2C systems.

Flexible Timing and Clock Support

A built-in programmable timer allows the DI2CM IP Core to operate across a wide range of system clock frequencies, simplifying integration into diverse SoC architectures without the need for external clocking logic. This flexibility ensures stable I2C timing across different FPGA families and ASIC process technologies.

SoC-Friendly Integration

The DI2CM IP Core is a technology-independent design that can be implemented in a variety of FPGA and ASIC processes. To support modern SoC architectures, the core can be delivered with the following host interfaces:

• AMBA APB

• AMBA AHB

• AMBA AXI

This scalability allows DI2CM to fit seamlessly into both deeply embedded systems and high-performance SoC platforms.

Typical Applications

• Embedded microcontroller-based systems

• System configuration and control

• Sensor and peripheral management

• Industrial and consumer electronics

• FPGA-based SoCs requiring I2C master functionality

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.co .

• Conforms to v.3.0 of the I2C specification
• Master operation
  • Master transmitter
  • Master receiver
• Support for all transmission speeds
  • Standard (up to 100 kb/s)
  • Fast (up to 400 kb/s)
  • Fast Plus (up to 1 Mb/s)
  • High Speed (up to 3,4 Mb/s)
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats on the I2C bus
• Interrupt generation
• Build-in 8-bit timer for data transfers speed adjusting
• Host side interface dedicated for microprocessors/microcontrollers
• User-defined timing (data setup, start setup, start hold, etc.)
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready