DI2CSB

DI2CSB IP Core – I2C Slave Bridge for Passive Devices in FPGA & ASIC

The DI2CSB IP Core from DCD-SEMI is a lightweight and efficient I2C slave bridge designed to connect passive target devices—such as memories, LCD displays, pressure sensors, and other peripherals—directly to an I2C bus in FPGA and ASIC designs. Delivered as a flexible bridge to APB, AHB, and AXI bus architectures, DI2CSB enables rapid and low-complexity integration of I2C-connected devices into modern SoC platforms.

The core operates as either a slave receiver or slave transmitter, with the operating mode automatically determined by the I2C master on the bus.

Zero-Configuration, Ready-to-Use Operation

A key advantage of the DI2CSB IP Core is its programming-free operation. The core requires no software configuration and is fully operational immediately after power-up or reset, making it ideal for simple, cost-sensitive, and low-power designs.

A very simple target interface, consisting only of read, write, and data signals, allows easy and direct connection to passive devices without complex control logic.

Automatic I2C Transaction Handling

DI2CSB automatically recognizes and handles standard I2C transactions, including:

• Read and write operations

• Burst read and burst write

• Repeated start conditions

All required protocol handling is performed in hardware, minimizing system complexity and CPU involvement.

Full I2C Specification Compliance

The DI2CSB IP Core incorporates all features required by the I2C specification and supports all standardized transmission modes:

• Standard mode – up to 100 kb/s

• Fast mode – up to 400 kb/s

• Fast Plus mode – up to 1 Mb/s

• High-Speed mode – up to 3.4 Mb/s

This ensures full compatibility with both legacy and high-performance I2C masters.

Technology-Independent and SoC-Friendly

Designed as a technology-independent IP Core, DI2CSB can be implemented across a wide range of FPGA and ASIC process technologies. For seamless SoC integration, the core can be delivered with:

• AMBA APB interface

• AMBA AHB interface

• AMBA AXI interface

Typical Applications

• Memory devices on I2C bus

• LCD and display controllers

• Sensor interfaces (pressure, temperature, environmental)

• Simple peripheral emulation

• FPGA-based SoCs requiring low-overhead I2C slave connectivity

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Conforms to the latest I2C specification
• Slave operation
  • Slave transmitter
  • Slave receiver
• Supports 3 transmission speed modes
  • Standard (up to 100 kb/s)
  • Fast (up to 400 kb/s)
  • Fast Plus (up to 1 Mb/s)
  • High Speed (up to 3,4 Mb/s)
• Allows operation from a wide range of input clock frequencies
• Support for reads, writes, burst reads, burst writes, and repeated start
• 7-bit addressing
• No programming required
• Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus