DI2CSB

DI2CSB bridge to APB, AHB, and AXI bus, provides an interface between a passive target device e.g. memory, LCD display, pressure sensors, etc., and the I2C bus. It can work as:

• a slave receiver or
• transmitter

depending on a working mode determined by the master device. A very simple interface, composed of reading, write, and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power-up/reset. Read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The solution incorporates all features required by the I2C specification. The DI2CSB supports the following transmission modes:

• Standard,
• Fast,
• Fast Plus, 
• High Speed.

The DI2CS is a technology-independent design and can be implemented in various process technologies.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Conforms to the latest I2C specification
• Slave operation
  • Slave transmitter
  • Slave receiver
• Supports 3 transmission speed modes
  • Standard (up to 100 kb/s)
  • Fast (up to 400 kb/s)
  • Fast Plus (up to 1 Mb/s)
  • High Speed (up to 3,4 Mb/s)
• Allows operation from a wide range of input clock frequencies
• Support for reads, writes, burst reads, burst writes, and repeated start
• 7-bit addressing
• No programming required
• Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus