DUSB2-ULPI

DUSB2-ULPI bridge to APB, AHB, and AXI bus, it is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, as well as state machines, to handle USB packets and transactions, endpoints number recognition logic, and endpoints FIFO control logic. The DUSB2-ULPI is designed to support:

• 12 Mb/s “Full Speed” (FS),
• 480 Mb/s “High Speed” (HS).

The design is technology independent and thus can be implemented in variety of process technologies. This core strictly conforms to the USB Specification v2.0 and ULPI v2.0. It is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Software configurable EP0 control endpoint size 8-64 bytes
• Software configurable 15 IN/OUT endpoints:
  • configurable number of endpoints
  • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
  • configurable direction of each endpoint
  • configurable size of each endpoint: 8-1024 bytes
• Supports ULPI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus