DUSB2-ULPI

DUSB2-ULPI – Full/High-Speed USB Peripheral Controller IP Core

The DUSB2-ULPI is a hardware implementation of a USB 2.0 full/high-speed peripheral controller, designed for seamless integration with ULPI bus transceivers. Optimized for FPGA and ASIC designs, this IP core handles all USB packet and transaction processing, including PID and address recognition, state machine control, endpoint number detection, and FIFO management.

Key Features:

• Supports 12 Mb/s Full-Speed (FS) and 480 Mb/s High-Speed (HS) operation.

• Interfaces with ULPI bus transceivers for high-speed USB PHY integration.

• Includes endpoint FIFO control logic for efficient data buffering.

• Technology-independent design, easily implemented across various process technologies.

• Fully compliant with USB Specification v2.0 and ULPI v2.0 standards.

• Delivered with a complete automated test bench for full SoC integration validation.

Benefits for Engineers:

• Streamlines high-speed USB peripheral integration with minimal CPU overhead.

• Reduces design complexity by providing ready-to-use hardware logic for packet processing.

• Ideal for FPGA or ASIC projects requiring ULPI PHY support.

• Ensures rapid development and testing with fully validated RTL and automated test suites.

Typical Applications:

• USB-based communication peripherals

• Mass storage devices

• Embedded USB controllers

• High-speed USB interface integration

DUSB2-ULPI is the ultimate solution for engineers looking to implement USB 2.0 peripherals with ULPI PHY support, delivering reliable performance and full compliance with modern USB standards.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Software configurable EP0 control endpoint size 8-64 bytes
• Software configurable 15 IN/OUT endpoints:
  • configurable number of endpoints
  • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
  • configurable direction of each endpoint
  • configurable size of each endpoint: 8-1024 bytes
• Supports ULPI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus