DUSB2

DUSB2 – Full/High-Speed USB 2.0 Peripheral Controller IP Core

The DUSB2 is a hardware implementation of a USB 2.0 full/high-speed peripheral controller that interfaces with a UTMI bus transceiver. This IP core provides a robust and efficient solution for FPGA and ASIC designs, handling all USB packet processing, PID and address recognition, endpoint management, and FIFO control logic.

Key Features:

• Supports 12 Mb/s Full-Speed (FS) and 480 Mb/s High-Speed (HS) USB 2.0 operation.

• Interfaces seamlessly with UTMI bus transceivers.

• Includes PID and address recognition logic for accurate USB communication.

• State machines manage USB packets and transactions efficiently.

• Endpoint number recognition logic and FIFO control for optimized data buffering.

• Technology-independent design suitable for multiple process technologies.

• Fully compliant with USB Specification v2.0.

• Delivered with a complete automated test bench for rapid SoC integration and validation.

Benefits for Engineers:

• Simplifies USB 2.0 peripheral integration in FPGA or ASIC designs.

• Reduces CPU overhead by offloading USB packet and endpoint processing to hardware.

• Accelerates development with fully validated RTL and automated test suites.

• Ensures compliance with USB standards for reliable device operation.

Ideal Applications:

• USB 2.0 peripherals for embedded systems

• Mass storage and communication devices

• Custom USB interface designs in FPGA or ASIC

DUSB2 provides engineers with a ready-to-use, high-performance USB 2.0 peripheral controller that minimizes design complexity and accelerates time-to-market.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Software configurable EP0 control endpoint size 8-64 bytes
• Software configurable 15 IN/OUT end-points:
  • configurable number of endpoints
  • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
  • configurable direction of each endpoint
  • configurable size of each endpoint: 8-1024 bytes
• Supports UTMI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• Simple interface allows easy connection to CPU
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus