DUSB2

DUSB2 bridge to APB, AHB, and AXI bus, it is a hardware implementation of a full/high-speed peripheral controller that interfaces to the UTMI bus transceiver. The IP Core contains the USB PID and addresses recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic, and endpoints FIFO control logic.

The DUSB2 is designed to support:

• 12 Mb/s “Full Speed” (FS)
• 480 Mb/s “High Speed”(HS).

The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v2.0. The DUSB2 core is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Software configurable EP0 control endpoint size 8-64 bytes
• Software configurable 15 IN/OUT end-points:
  • configurable number of endpoints
  • configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
  • configurable direction of each endpoint
  • configurable size of each endpoint: 8-1024 bytes
• Supports UTMI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• Simple interface allows easy connection to CPU
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus