PSRAM Memory Controller IP

Boost Your PSRAM Designs with DCD-SEMI’s HyperBus™ Memory Controller IP!

Need high-speed, low-pin-count access to HyperRAM™? Our new IP Core supports HyperBus™ and xSPI (JESD251A) protocols, delivering up to 200 MHz performance with full AXI, AHB, and APB compatibility.

✅ HyperRAM™-ready
✅ OCTAL SPI master/slave
✅ DMA support
✅ Fully configurable & FPGA/ASIC-friendly

Perfect for embedded and SoC designs needing fast, reliable PSRAM control — backed by DCD-SEMI’s trusted IP quality.

DCD-SEMI’s HyperBus™ Memory Controller IP Core delivers high-speed, low-pin-count access to HyperRAM™ and PSRAM devices, perfect for embedded, SoC, and FPGA designs. Built on our proven DFSPI architecture, this IP core supports SINGLE, DUAL, QUAD, and OCTAL SPI master/slave modes, with optional HyperBus™ and xSPI (JESD251A) protocol compatibility for modern memory systems.

Key Advantages for Design Engineers:

• HyperRAM™ & xSPI Ready: Full support for the latest HyperBus™ memory and xSPI standard devices.

• High Performance: Up to 200 MHz clock speed, ensuring maximum memory throughput for high-bandwidth applications.

• Flexible Bus Integration: Seamlessly bridges AXI, AHB, and APB interfaces for easy system integration.

• Fully Configurable SPI Parameters: Adjustable SCK polarity, phase, and timing for optimized performance.

• OCTAL SPI & Multi-I/O Modes: Efficient data transfer using Single, Dual, Quad, and Octal SPI modes.

• DMA Support: Single and multi-transfer modes for high-speed memory access with minimal CPU load.

• Technology-Independent HDL: Portable across FPGA and ASIC platforms for diverse hardware projects.

• Automatic Slave Select Control: Handles multiple SPI slaves via SSCR, reducing software overhead.

Why Choose DCD-SEMI:

• Simplifies PSRAM/HyperRAM integration in modern SoC and FPGA designs.

• Optimized for low-latency memory access in Execute-in-Place (XIP) architectures.

• Offers robust reliability and customizable configurations to match any system requirements.

• Provides a low-pin-count solution for cost- and space-sensitive applications.

With DCD-SEMI’s HyperBus™ Memory Controller, engineers can unlock the full potential of high-speed PSRAM, streamline integration into modern SoCs, and deliver reliable, high-performance memory access in embedded systems.

This IP core is a drop-in solution for developers looking to boost system performance with HyperRAM™/PSRAM, offering ease of use, configurability, and the trusted reliability of DCD-SEMI’s IP design. Whether you’re building an embedded device or a complex SoC, our HyperBus™ Memory Controller provides the speed and flexibility you need.

DCD-SEMI’s advanced HyperBus™ Memory Controller IP Core is a versatile, high-performance solution designed for seamless integration into modern SoCs and FPGA-based systems. Based on our proven DFSPI architecture, this controller bridges easily to APB, AHB, and AXI buses and supports SINGLE, DUAL, QUAD, and OCTAL SPI master/slave modes — making it ideal for a wide range of embedded applications.

This fully configurable SPI controller includes optional support for the HyperBus™ memory protocol and xSPI (Expanded Serial Peripheral Interface – JESD251A), enabling high-speed communication with the latest generation of HyperRAM™ and NOR/NAND Flash memories. The controller also features adjustable serial clock polarity and phase (SCK), ensuring compatibility with a broad array of SPI-based devices.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• NOR & NAND Flash Memory Support
• Set of software-accessible control registers to execute any Flash memory command
• Supports any device clock frequency, polarity, and phase,
• Programmable baud rate generator,
• Built-in FLASH Commands decoder supports most popular FLASH devices,
• Optional built-in AES Encoder/Decoder
• DMA support
• Optional support for various SPI Bus Standards: HyperBus^TM, xSPI
• Compliant with AMBA2 Specification, support APB, AHB, AXI bus interfaces
• Single, Dual, Quad and OCTAL SPI transfer/reception
• Execute in place – XIP functionality support
• Data Bus Size configuration to 8, 16, or 32 bits wide
• Optional FIFO size extension
• Maximum supported Flash address range – 32 bits
• Up to 4 SPI slaves can be addressed
  • Software Slave Select Output – SSO – selection
  • Automatic Slave Select outputs assertion
• System error detection
• Interrupt generation
• Bit rates are generated as 1/ 2.. 1/255 of the system clock.
• Four SPI transfer formats supported: CPOL/CPHA.
• A simple interface allows easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states