D16550

D16550 UART IP Core – FIFO-Based UART for FPGA & ASIC Designs

The D16550 UART IP Core from DCD-SEMI is a proven Universal Asynchronous Receiver/Transmitter (UART) designed for seamless FPGA and ASIC integration. Delivered as a flexible bridge to APB, AHB, and AXI bus architectures, the D16550 is functionally identical to the TL16C550A, ensuring full compatibility with existing software and drivers.

The core supports serial communication in both standard UART mode and FIFO mode, making it an ideal solution for legacy UART replacement and moderate-throughput embedded systems.

FIFO-Based Data Transfer with Reduced CPU Load

In FIFO mode, the D16550 activates internal buffers allowing:

• 16-byte transmit FIFO

• 16-byte receive FIFO, with 3 bits of error status per byte

FIFO buffering significantly reduces interrupt frequency compared to classic 16450 UARTs, improving overall system efficiency while preserving legacy behavior.

Complete Status Visibility and Robust Error Detection

The processor can read the full UART status at any time during operation. Status reporting includes:

• Transfer state and FIFO conditions

• Parity, overrun, framing, and break error detection

• Interrupt source identification

This enables predictable serial communication and simplifies firmware development and debugging.

Programmable Baud Rate and Accurate Timing

The D16550 integrates a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (2¹⁶ − 1), generating a 16× clock for the internal transmitter logic. The same clock can also be used to drive the receiver logic.

A dedicated BAUD CLK input allows designers to set an exact transmission speed, while the UART core logic continues to operate at the CPU clock frequency—simplifying clock-domain integration and timing closure.

MODEM Control and Programmable Interrupts

The core includes full MODEM control functionality and a programmable interrupt system, allowing efficient interrupt-driven communication. Interrupt behavior can be tailored to application requirements, minimizing CPU overhead and eliminating unnecessary polling.

Configurable Architecture for Area Optimization

During synthesis, the D16550 offers fine-grain configurability, allowing designers to:

• Enable or disable MODEM control logic

• Enable or disable FIFO buffers

• Adjust FIFO depth

In area-constrained designs where FIFO and MODEM features are not required, disabling these blocks allows up to ~50% logic resource savings, effectively operating the core in 16450-compatible mode.

Optimized for SoC and Multi-UART Designs

The D16550 is ideal for systems where the UART and microcontroller share the same clock domain inside an FPGA or ASIC. Its universal interface simplifies implementation and verification by reducing clock tree complexity.

The core is also well suited for standalone multi-UART designs, where several UART instances are integrated within a single chip and connected to off-chip devices.

Verification-Ready and Technology Independent

Like all DCD-SEMI UART IP Cores, the D16550 includes a fully automated testbench with a complete test suite, enabling straightforward validation throughout every stage of the SoC design flow.

The IP Core is technology-independent and can be implemented across a wide range of FPGA and ASIC process technologies.

Typical Applications

• 16550 / TL16C550A UART replacement

• Embedded SoCs and microcontroller subsystems

• Industrial and instrumentation systems

• FPGA-based multi-UART designs

• Legacy system modernization projects

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Selection Guidelines

• Choose D16450 for exact legacy 16450 / TL16C450 replacement.
• Choose D16550 when FIFO buffering and moderate CPU optimization are required.
• Choose D16950 for high-performance UART with deep FIFO and low CPU load.
• Choose D8530 when dual-channel USART and legacy protocol support are required.
• Choose DMESCC for advanced multiprotocol serial communication and block handling.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with 16450 and 16550 UARTs
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Supports RS232 and RS485 standards (optional)
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Fully programmable serial interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd or no-parity bit generation and detection
  • 1-, 1 ½-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states