D16950

D16950 bridge to APB, AHB, AXI bus, it is a soft core of a Universal Synchronous and Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read the complete status of the UART at any time during the functional operation. The reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16950 includes a programmable baud rate generator which is able to divide a timing reference clock input by divisors of 1 to (216-1) and produce an n × clock for driving internal transmitter logic. Provisions are also included to use this n × clock to drive receiver logic. We also equipped our core with complete MODEM-control capability and a processor-interrupt system. Interrupts can be programmed according to your requirements, minimizing the computing required to handle the communications link. The D16950 core includes all (16450, 16550, 16650 and 16750) features and additional functions. The D16950 has ICR registers which give additional capabilities of UART work configuration. Data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or DSR (only for receiver) pin. The NMR register allows 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127. In the FIFO mode, there is a selectable autoflow control feature that can reduce software overload significantly and automatically increase system efficiency by controlling serial data flow through the RTS output and CTS input signals. The Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. Like all our UART Cores, the D16950 includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. This efficient solution is a technology-independent design that can be implemented in a variety of process technologies.

Watch the D16950 presentation on DCD’s YouTube:

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
• Synchronous and Asynchronous transmission
• Configuration capability
• Supports RS232 and RS485 standards
• Separate configurable BAUD clock line
• Supports IRDA data format mode
• Majority Voting Logic
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• FIFO size – 128 Bytes
• Optional FIFO size extension to 256 or 512 Bytes
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
• Programmable Hardware Flow Control through RTS and CTS
• Programmable Flow Control using DTR and DSR
• Programmable in-band Flow Control using XON/XOFF
• Programmable special characters detection
• Trigger levels for TX and RX FIFO
• Interrupts and automatic in-band and out-off-band flow control
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, 8- or 9-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1.5-, or 2-stop bit generation
  • Internal baud generator
  • Detection of bad data in receiver FIFO
• Clock prescaler from 1 to 31,875
• Enhanced isochronous clock option
• 9- bit data mode
• Software reset
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states