D16750

D16750 UART IP Core – High-Performance TL16C750-Compatible UART

The D16750 UART IP Core from DCD-SEMI is a high-performance Universal Asynchronous Receiver/Transmitter (UART) designed for FPGA and ASIC integration. Delivered as a bridge to APB, AHB, and AXI bus architectures, the D16750 is functionally identical to the TL16C750, making it ideal for legacy UART replacement and high-throughput embedded systems.

Deep FIFO Buffers for Maximum Throughput

The D16750 supports serial communication in both UART and FIFO modes. In FIFO mode, internal buffers allow up to:

• 512-byte transmit FIFO

• 512-byte receive FIFO, including 3 bits of error status per byte

This deep buffering drastically reduces CPU overhead and ensures reliable high-speed serial data transfer in demanding applications.

Full Status Reporting and Error Detection

The processor can read the full UART status at any time during operation. The reported status includes:

• Transfer operation state and FIFO condition

• Parity, overrun, framing, and break error detection

• Interrupt source information

This enables deterministic communication and simplifies firmware integration.

Programmable Baud Rate and Flexible Clocking

The D16750 integrates a programmable baud rate generator capable of dividing a reference clock by divisors from 1 to (2¹⁶ − 1), generating a 16× internal transmitter clock. The same clock can also drive the receiver logic.

A dedicated BAUD CLK input allows exact transmission speed settings, while the core logic runs at the CPU clock frequency, simplifying timing closure and system integration.

MODEM Control and Intelligent Interrupts

The core includes full MODEM control functionality and a programmable interrupt system, which allows interrupts to be tailored to application requirements, minimizing CPU load.

In FIFO mode, the D16750 also offers selectable autoflow control via RTS/CTS signals, automatically regulating serial data flow for higher system efficiency.

Configurable Architecture for Area Optimization

During synthesis, designers can enable or disable MODEM control logic and FIFOs or adjust FIFO depth. In area-constrained designs, disabling unused features can reduce logic utilization by up to 50%, effectively operating the core in 16450-compatible mode.

Ideal for SoC and Multi-UART Designs

The D16750 is perfect for systems where the UART and microcontroller share the same clock domain inside an FPGA or ASIC. Its universal bus interface reduces clock-tree complexity and simplifies verification.

It is also suited for standalone multi-UART implementations, where multiple UARTs are integrated within a single chip and connected to off-chip devices.

Verification-Ready and Technology Independent

Like all DCD-SEMI UART IP Cores, the D16750 comes with a fully automated testbench and complete set of tests, enabling straightforward SoC-level validation.

The IP Core is technology-independent and can be implemented across a wide range of FPGA and ASIC process technologies.

Typical Applications

• TL16C750 / high-performance UART replacement

• High-speed embedded SoCs

• Industrial, telecom, and instrumentation systems

• FPGA-based multi-UART designs

• High-throughput serial communication applications

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Selection Guidelines

• Choose D16450 for exact legacy 16450 / TL16C450 replacement.
• Choose D16550 when FIFO buffering and moderate CPU optimization are required.
• Choose D16750 for high-performance legacy replacement with deep FIFO and low CPU load.
• Choose D16950 for high-throughput UART with deep FIFO, synchronous mode, and advanced flow control.
• Choose D8530 when dual-channel USART and legacy protocol support are required.
• Choose DMESCC for advanced multiprotocol serial communication and block handling.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

• Software compatible with 16450, 16550 and 16750 UARTs
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Supports RS232 and RS485 standards
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 64 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Configurable FIFO size allowing up to 512 levelsdeep FIFOs in both Rx and Tx directions.
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Programmable automatic Hardware Flow Control logic through Auto-RTS and Auto-CTS
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1.5-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable