CAN FD

Introducing DCD’s Ingenious CAN FD IP Core: Empowering Engineers with Unparalleled Flexibility.

When it comes to seamlessly infusing cutting-edge Controller Area Network (CAN) capabilities into diverse systems, look no further than DCD’s CAN FD IP Core. This engineering marvel can be harnessed as a standalone powerhouse, an integral part of an ASIC, or an FPGA marvel. Guided by the ISO11898-1:2015 standard, it ushers in flawless communication aligned with industry-favorite protocols, making it a game-changer for engineers and innovators.

Engineered to cater to both Classical CAN and the dynamic CAN FD, this module does require external transceiver hardware to establish a tangible link to the CAN bus. Our ingenious approach employs a single or dual-ported Message RAM, strategically situated outside the module, connected through the versatile Generic Master Interface. This meticulous design simplifies the art of message handling, ensuring efficiency at every turn.

The pièce de résistance? Seamlessly uniting the host CPU with the CAN FULL IP Core module via the 32-bit Generic Interface. This harmonious partnership guarantees a frictionless fusion, orchestrating a symphony of data exchange. But we don’t stop there. Compatibility is our middle name, as our Core seamlessly supports a roster of interface wrappers including, but not limited to:

• AMBA – APB / AHB / AXI Lite Bus
• Altera Avalon Bus
• Xilinx OPB Bus

Variety is the spice of engineering life, and that’s why our IP core shines in two tantalizing flavors: the dynamic Basic and the robust Safety-Enhanced.

Prepare to be awestruck – our ingenious creation is not just an IP core; it’s a safety-critical masterpiece designed as an ISO26262-10 Safety Element out of Context. As if that’s not impressive enough, it can be amped up with vital safety mechanisms, complete with comprehensive ISO26262 soft IP SEooC work products. Expect nothing less than a complete Failure Modes Effects and Detection Analysis (FMEDA) – a guidebook that unravels seamless IP integration into your unique system, and a roadmap to conduct meticulous system-level safety analysis.

As for the skeptics, rest assured. We’ve subjected our safety-related work products to a third-party, independent audit, elevating our masterpiece’s trustworthiness.

Safety metrics? Oh, they are more than met. Both IPs boast an Automotive Safety Integrity Level (ASIL-B), with the Single Point Fault Metric (SPFM) soaring past 90% and the Latent Fault Metric (LFM) comfortably exceeding 60%. In simple terms – they’re bulletproof.

But wait, there’s more. Our ASIL-B ready design seamlessly slides into Automotive Safety Systems at the ASIL-B level, but here’s the kicker: we’ve got higher ASIL-level ready IP in our arsenal, if you dare to dream bigger.

Curiosity piqued? Dive into this engineering marvel by reaching out to our support team. Let the innovation begin!

CAN FuSa white papers

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Designed in accordance with ISO 11898‐1:2015 specification
• Supports CAN and CAN FD frames
• Supports up to 64 bytes of data frame
• Flexible data rates supported
• AUTOSAR support
• SAE J1939 support
• Simple 8/16/32‐bit CPU slave interface
• Data rate up to 8Mbps
• Up to 128 Base ID filters
• Up to 64 Extended ID filters
• 2 Configurable receive FIFO
• Up to 64 dedicated Receive Buffers
• Overload frame is generated on FIFO overflow
• Up to 32 dedicated Transmit Buffers
• Configurable Transit Buffers to FIFO or QUEUE
• Configurable Transmit Event FIFO
• Normal, Listen Only and Loopback modes supported
• Transmitter Delay Compensation up to three data bits long
• Ability to abort transmission
• Readable error counters
• Last Error Code
• Timestamp according to CiA 603 support
• Two configurable interrupt lines
• Two clock domains (CAN clock and CPU clock)
• Fully synthesizable
• Static synchronous design with positive edge clocking and synchronous reset
• No internal tri‐states
• Scan test ready