DPSI5 IP Core — High-Reliability PSI5 Controller for Automotive Sensors

Advanced Peripheral Sensor Interface (PSI5) for ECUs

The DPSI5 IP Core from DCD-SEMI is a hardware implementation of the Peripheral Sensor Interface (PSI5) protocol, fully compliant with PSI5 specification V2.3. Designed for integration into Electronic Control Units (ECUs), DPSI5 enables reliable communication with up to six automotive sensors per bus, supporting advanced applications from airbags to vehicle dynamics and pedal angle sensors.

Data transmission from sensors to the ECU uses current modulation on the power supply line at 125 kbit/s or 189 kbit/s, decoded via Manchester coding. Transmission from the ECU to sensors is achieved through voltage modulation, ensuring robust, low-latency communication.

DPSI5 supports both asynchronous and synchronous operation, with flexible data word lengths ranging from 8 to 28 bits, and ensures message integrity via CRC checks or bit parity.

Key Features of DPSI5 IP Core

• Two-Wire Current Interface: Simplified wiring for power and data reduces system cost and complexity

• Manchester-Coded Digital Data Transmission: Ensures synchronization, robustness, and EMI resilience

• High-Speed Data Transmission: Supports 125 kbps, with optional 189 kbps mode for higher-performance sensors

• High Electromagnetic Compatibility (EMC): Low-impedance design provides excellent resistance to EMI

• Flexible Data Frames: Supports variable data word lengths (8–28 bits) for diverse sensor requirements

• Asynchronous & Synchronous Modes: ECU-controlled or sensor-initiated communication

• Multi-Sensor Bus Configurations: Up to six sensors per PSI5 bus, supporting both point-to-point and bus setups

Advantages of PSI5

• Cost Efficiency: Minimal cabling and connectors reduce overall system costs

• High Reliability: Proven for critical applications like airbags, accelerator pedals, and acceleration sensors

• Flexibility: Adaptable for various sensor types and automotive applications

Integrating the DPSI5 IP Core allows manufacturers to build highly reliable, cost-effective automotive sensor systems while maintaining robust performance in harsh environments.

Safety-Enhanced Design with ISO 26262 Compliance

The DPSI5 IP Core is available in:

• Basic Version — for standard automotive sensor communication

• Safety-Enhanced Version — developed as an ISO26262-10 Safety Element out of Context (SEooC)

The Safety-Enhanced variant includes optional functional safety mechanisms, complete FMEDA analysis, and step-by-step integration guidance to support system-level safety analysis. All work products have undergone third-party independent audits, ensuring reliability and compliance.

ASIL-B Ready for Automotive Safety Systems

Safety metrics demonstrate compliance with ASIL-B:

• SPFM > 90% (Single Point Fault Metric)

• LFM > 60% (Latent Fault Metric)

The DPSI5 IP Core is ready for integration into ASIL-B automotive systems, with optional availability for higher ASIL-level designs upon request.

Why Choose DCD-SEMI DPSI5 IP Core

• PSI5 V2.3 compliant for automotive sensors

• Supports 125 kbps and 189 kbps data rates

• Up to six sensors per bus

• Flexible 8–28 bit data frames, asynchronous/synchronous operation

• High EMC robustness and reliability

• FPGA & ASIC ready

• Safety-Enhanced version with ISO26262 SEooC compliance

• ASIL-B ready, with optional higher ASIL-level support

DPSI5, LIKE ALL DCD’S IP CORES, IS TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For technical specifications, integration support, or safety-enhanced options, contact info@dcd-semi.com

• Supports bidirectional communication between ECU-to-sensor
• Asynchronous or synchronous operation
• Manchester decoder digital data transmission
• Data transmission speed 125Kbit/s or 189 Kbit/s
• Support up to 6 time slots between SYNC pulses
• Configurable data word length from 8 to 28 bits
• Configurable type of frame checking each slot
• CRC or parity checking
• 24 bits time stamp
• Configurable RX FIFO
• Fully synthesizable
• Static synchronous design with positive edge clocking and synchronous reset
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Lite Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus