D2698 Octal UART IP Core – High-Density Multi-Channel UART

Description

D2698 – Octal UART IP Core for High-Density Serial Communication

The D2698 Octal UART IP Core from DCD-SEMI is a high-performance, technology-independent solution for implementing multi-channel UART communication in FPGAs and ASICs. Fully software compatible with the SC2698, the D2698 provides eight full-duplex asynchronous receiver/transmitter channels in a single core, making it ideal for high-density applications such as telecom gateways, industrial clusters, and multi-UART embedded systems.

Key Features:

Octal UART: 8 independent UART channels for simultaneous serial communication.
FIFO Support: Each channel includes a 3-character receiver FIFO, reducing CPU overhead.
Flexible Clocking: Each channel’s receiver and transmitter speed can be programmed independently using one of 26 fixed baud rates, a 16× clock from a programmable counter/timer, or an external 1X or 16X clock.
Extended Baud Rate: Built-in baud rate generator supports high-speed serial interfaces.
Interrupt System: Programmable receiver and transmitter interrupts allow efficient polled or interrupt-driven operation.
Modem Interface Support: Provides robust modem control for complex serial systems.
Independent Channel Configuration: Operating mode and data format of each channel can be configured separately, enabling dual-speed and multi-protocol applications.
Technology-Independent Design: Compatible with a wide range of FPGA and ASIC process technologies, simplifying SoC integration.

Applications:

High-density embedded UART systems
Clustered terminal and industrial communication systems
Telecom and networking gateways
Multi-UART ASIC and FPGA designs

Why Choose DCD-SEMI D2698:
The D2698 is specifically designed to minimize CPU load, provide independent channel configuration, and support high-density serial communication in a single, compact IP core. Its flexible clocking options and programmable baud rates make it ideal for modern multi-UART systems, offering both performance and integration efficiency.

Bus Interfaces: APB, AHB, AXI

Technology Independent: Yes – suitable for FPGA and ASIC implementations

Feature / IP Core	D2692	D2694	D2698
Core Type	Dual UART (DUART)	Quad UART (QUART)	Octal UART (OUART)
Channels	2 full-duplex	4 full-duplex	8 full-duplex
FIFO Size	8-character RX/TX	8-character RX/TX	8-character RX/TX
Watchdog Timer	Yes, per receiver	Yes, per receiver	Yes, per receiver
Mode Register 0	Yes	Yes	Yes
Extended Baud Rate	Yes	Yes	Yes
Programmable Interrupts	Receiver & transmitter	Receiver & transmitter	Receiver & transmitter
Modem Interface	Yes	Yes	Yes
DMA Support	Yes	Yes	Yes
Independent Channel Speed	Yes	Yes	Yes
Clocking Options	Fixed, 16× derived, external	Fixed, 16× derived, external	Fixed, 16× derived, external
Polled / Interrupt Operation	Supported	Supported	Supported
Software Compatibility	SC26C92, SCC2692, SCN2681	SC2694	SC2698
Key Applications	Dual-speed terminals, embedded systems	Multi-UART clusters, industrial systems	High-density multi-UART systems, telecom, gateways
Bus Interfaces	APB, AHB, AXI	APB, AHB, AXI	APB, AHB, AXI
Technology Independence	Yes	Yes	Yes

Notes:

D2692: Dual-channel UART for simpler embedded applications or legacy SC26C92 replacement.
D2694: Quad-channel UART suitable for clustered terminals or medium multi-UART systems.
D2698: Octal UART designed for high-density, high-throughput serial communication applications.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

D2698 ASIC
D2698 INTEL FPGA
D2698 LATTICE
D2698 MICROSEMI
D2698 XILINX

Key features

Software compatible with SCC2698 UART
Configuration capability
8 full-duplex independent asynchronous receiver/transmitters
3 character FIFOs for each receiver channel
Programmable data format:
- 5 to 8 data bits plus parity
- Odd, even, no parity or force parity
- 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
16-bit programmable Counter/Timer
Programmable baud rate for each receiver and transmitter selectable from:
- 26 fixed rates: 50 to 115.2k baud
- Programmable user-defined rates derived from a programmable counter/timer
- External 1X or 16X clock
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode:
- Normal (full-duplex)
- Automatic echo
- Local loopback
- Remote loopback
2 Multi-function input and 2 I/O ports:
- Can serve as clock, modem, or control inputs
- Change of state detection on four inputs
Multi-function output port:
- Individual bit set/reset capability
- Outputs can be programmed to be status/interrupt signals
- FIFO states for DMA and modem interface
Versatile interrupt system:
- Single interrupt output with eight maskable interrupting conditions
- Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
- Each FIFO can be programmed for four different interrupt levels
- Watchdog timer for each receiver
Maximum data transfer rates: 1X – 1Mb/sec, 16X – 1Mb/sec
Start-end break interrupt/status
Detects break which originates in the middle of a character
Power down mode
Receiver timeout mode
Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus

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