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D2692

Dual Channel UART

Description

D26C92 Dual UART IP Core – SC26C92 / SCC2692 / SCN2681 Compatible

The D26C92 UART IP Core from DCD-SEMI is a high-performance dual-channel Universal Asynchronous Receiver/Transmitter (DUART) designed for FPGA and ASIC integration. Delivered as a bridge to APB, AHB, and AXI bus architectures, it is software compatible with SC26C92, SCC2692, and SCN2681, offering additional features and enhanced FIFOs for demanding serial communication applications.

Dual-Channel Full-Duplex Communication

The D26C92 provides two independent full-duplex UART channels in a single core:

  • Each channel includes 8-character receive and transmit FIFOs

  • Mode register 0 and extended baud rate support

  • Independent receiver and transmitter configuration for flexible multi-speed operation

  • Optional DMA and modem interface support

This makes the D26C92 ideal for dual-speed channel applications, such as clustered terminal systems or multi-protocol communication interfaces.

Programmable Baud Rate and Timing Control

Each channel can select its operating speed from 27 fixed baud rates, a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock.

  • Baud rate generator supports both crystal and external clock inputs

  • Independent speed configuration allows simultaneous operation at different baud rates per channel

This flexibility makes it highly suitable for complex multi-device serial networks.

Advanced Interrupt and Watchdog Support

The D26C92 core includes:

  • Programmable receiver and transmitter interrupts for efficient CPU offload

  • Watchdog timer for each receiver to ensure data integrity

  • Polled or interrupt-driven operation to fit a variety of embedded system architectures

FIFO-Enhanced Architecture

The built-in FIFOs improve system performance by reducing CPU intervention during high-speed data transmission:

  • 8-character depth for both RX and TX FIFOs

  • Handles high-throughput communication with low CPU load

  • Supports dual-speed channel operation for multi-device systems

Flexible and Configurable Interfaces

The D26C92 core is fully configurable to meet project-specific requirements:

  • Each channel can operate independently with different baud rates and data formats

  • Supports full-duplex operation, modem interface, and DMA transfers

  • Compatible with standard APB, AHB, and AXI interfaces

Ideal Applications

  • Dual-speed terminal clusters and legacy system upgrades

  • Industrial automation and control systems

  • Multi-protocol communication devices

  • FPGA and ASIC SoC designs requiring dual UART channels

  • Systems requiring software-compatible SC26C92 / SCC2692 / SCN2681 replacement

Verification-Ready and Technology Independent

Like all DCD-SEMI UART IP Cores, the D26C92 includes a fully automated testbench and complete validation suite, enabling quick integration into SoC and FPGA designs.

  • Technology-independent design suitable for a wide range of FPGA and ASIC process nodes

  • Optimized for low logic utilization and high throughput

 

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Feature / IP Core D16450 D16550 D16750 D16752 D16950 D8530 DMESCC D26C92
Primary Function Classic UART FIFO-based UART High-performance UART Dual-channel high-performance UART High-throughput UART Dual-channel USART Dual-channel multiprotocol serial controller Dual-channel UART / DUART
UART Compatibility 16450 / TL16C450 16550 / TL16C550A 16750 / TL16C750 16752 / TL16C752 16450–16750 + OX16C950 Zilog 8530–compatible Enhanced ESCC-compatible SC26C92 / SCC2692 / SCN2681 compatible
Channels 1 1 1 2 1 2 2 2
Supported Modes Asynchronous Asynchronous & FIFO Asynchronous & FIFO Asynchronous & FIFO, dual-channel Asynchronous & synchronous Asynchronous & synchronous Asynchronous & synchronous Asynchronous & FIFO, dual-channel
FIFO Support ❌ No FIFO ✅ 16-byte FIFO ✅ 512-byte FIFO ✅ 64-byte FIFO per channel ✅ 128-byte FIFO Optional / limited Optional / configurable ✅ 8-character RX/TX FIFO per channel
FIFO Trigger Levels — Configurable Programmable (1–512) Programmable per channel Programmable (1–127) — — Programmable per channel
CPU Load High Medium Low Low Low Medium Medium Medium
Error Reporting Parity, framing, overrun, break Parity, framing, overrun, break Parity, framing, overrun, break Parity, framing, overrun, break, idle Parity, framing, overrun, break Parity, CRC, abort Parity, CRC, abort Parity, framing, overrun, break
CRC Generation / Check No No No No No Yes (sync modes) Yes (sync modes) No
Modem Control Full Full Advanced autoflow Hardware/software flow control, TCR Advanced autoflow Yes (both channels) Yes (both channels) Yes, DMA & modem interface
Interrupt System Programmable Programmable Advanced programmable Programmable, FIFO RDY register Advanced programmable Programmable Programmable Programmable, independent per channel
DMA Support Interrupt-optimized Interrupt-optimized Yes Yes Yes Yes Yes Yes
Clocking Options Internal BRG Internal BRG Internal / external Internal / external Internal / external Internal BRG Internal BRG Independent programmable clock, external or 16× derived
Special Features Legacy compatibility Configurable FIFO & Modem Deep FIFO (512B), autoflow, 16450 modes Dual-channel, FIFO RDY register, hardware/software flow control, TCR Deep FIFO, 9-bit mode, synchronous Legacy protocol support (HDLC, SDLC) Enhanced block transfer, vectored interrupts Independent channel baud rates, watchdog timers, dual-speed operation
Typical Applications Legacy UART replacement FIFO-based legacy upgrade High-throughput UART, legacy replacement Dual-channel embedded UART, TL16C752 replacement Telecom, industrial gateways Telecom, LAN, industrial serial Communications controllers, protocol engines Dual-speed terminals, embedded dual UART systems, SC26C92 replacement
Bus Interfaces APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI APB, AHB, AXI
Technology Independence Yes Yes Yes Yes Yes Yes Yes Yes

Selection Guidelines

  • Choose D16450 for exact legacy 16450 / TL16C450 replacement.
  • Choose D16550 when FIFO buffering and moderate CPU optimization are required.
  • Choose D16750 for high-performance legacy replacement with deep FIFO and low CPU load.
  • Choose D16752 for dual-channel high-performance UART with hardware/software flow control and 64-byte FIFOs.
  • Choose D16950 for high-throughput UART with deep FIFO, synchronous mode, and advanced flow control.
  • Choose D8530 when dual-channel USART and legacy protocol support are required.
  • Choose DMESCC for advanced multiprotocol serial communication and block handling.
  • Choose D26C92 for dual-channel SC26C92 / SCC2692 / SCN2681 replacement with independent baud rates, watchdog timers, and FIFO support.

 

Watch the D2692 presentation on DCD’s YouTube:

Subskrybuj mój kanał w YouTube

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

Download full specification

D2692 ASIC
D2692 INTEL FPGA
D2692 LATTICE
D2692 MICROSEMI
D2692 XILINX

Key features

  • Software compatible with SC26C92, SCC2692 and SCN2681 UARTs
  • Configuration capability
  • Dual full-duplex independent asynchronous receiver/transmitters
  • 8 character FIFOs for each receiver and transmitter
  • Programmable data format:
    • 5 to 8 data bits plus parity
    • Odd, even, no parity or force parity
    • 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
  • 16-bit programmable Counter/Timer
  • Programmable baud rate for each receiver and transmitter selectable from:
    • 27 fixed rate
    • Other baud rates – at 16X
    • Programmable user-defined rates derived from a programmable counter/timer
    • External 1X or 16X clock
  • Parity, framing, and overrun error detection
  • False start bit detection
  • Line break detection and generation
  • Programmable channel mode:
    • Normal (full-duplex)
    • Automatic echo
    • Local loopback
    • Remote loopback
    • Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
  • Multi-function 7-bit input port:
    • Can serve as clock, modem, or control inputs
    • Change of state detection on four inputs
  • Multi-function 8-bit output port:
    • Individual bit set/reset capability
    • Outputs can be programmed to be status/interrupt signals
    • FIFO states for DMA and modem interface
  • Versatile interrupt system:
    • Single interrupt output with eight maskable interrupting conditions
    • Output port can be configured to provide a total of up to six separate wire-ORable interrupt outputs
    • Each FIFO can be programmed for four different interrupt levels
    • Watch dog timer for each receiver
  • Automatic wake-up mode for multidrop applications
  • Start-end break interrupt/status
  • Detects break which originates in the middle of a character
  • Power down mode
  • Receiver timeout mode
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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