DIRDA

DIRDA - versatile support for widely used IR transmission protocols.

DIRDA IP Core – Infrared Receiver Decoder for FPGA & ASIC Designs

The DIRDA IP Core from DCD-SEMI is a compact and efficient infrared (IR) receiver controller designed to perform serial-to-parallel conversion of data received from an IR receiver diode. Optimized for FPGA and ASIC implementations, DIRDA enables reliable decoding of popular and custom IR remote-control protocols while significantly reducing processor workload.

The core allows the processor to read full status information at any time during operation, ensuring deterministic control and easy system integration.

Flexible Timing and Low CPU Overhead

DIRDA integrates a programmable internal prescaler that divides the reference timing clock by values from 1 to 128, generating an optimized internal clock for the receiver logic. This flexibility allows accurate decoding across a wide range of IR carrier frequencies and protocols.

To further minimize CPU involvement, the core features a fully programmable interrupt system. Interrupts can be configured to match application-specific requirements, reducing polling overhead and improving overall system efficiency.

Dual Operating Modes for Maximum Versatility

The DIRDA IP Core supports two distinct operating modes:

MODE0 – Full Frame Decoding

• Decodes the entire IR frame in hardware

• Detects transmission errors

• Identifies key release events

MODE1 – FIFO-Based Symbol Capture

• Activates an internal FIFO buffer

• Stores up to 32 received symbols

• Programmable interrupt trigger level (1–32 symbols)

This dual-mode architecture enables both fully autonomous decoding and raw symbol processing, depending on system requirements.

Interface Options and SoC Integration

DIRDA can be delivered with:

• Small 8-bit SRAM-like interface for minimal systems

• AMBA APB slave interface for modern SoC designs

The core is fully compatible with technology-independent FPGA and ASIC flows.

Supported and Target IR Protocols

DIRDA is an ideal solution for implementing widely used IR protocols, including:

• NEC

• SIRC (Sony IR)

• TC9012

• Custom and non-standard IR protocols

Typical Applications

• IR remote control receivers

• Consumer electronics (TVs, set-top boxes, audio devices)

• Industrial control panels

• FPGA-based embedded systems

• ASIC designs requiring low-power IR decoding

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Enabling and disabling controller via register
• Two working modes:
  • MODE0 ‐ standard IR protocols decoding
  • MODE1 ‐ symbols width detection for any standard or non‐standard IR data format
• Support for any configuration of the following protocols (MODE0):
  • NEC with Simple Repeat Code
  • NEC with Full Repeat Code
  • TC9012 data format
  • SIRC (SONY)
• Support for masked and not masked interrupts:
  • Symbol overflow interrupt (MODE1)
  • Symbol timeout interrupt (MODE1)
  • Symbol received interrupt (MODE1)
  • Key release interrupt (MODE0)
  • Data overflow interrupt (MODE0)
  • Data frame format error interrupt (MODE0)
  • Data received interrupt (MODE0)
• Interrupts flags clearance via write to register
• Configurable reset
• Configurable data bus width
• Reference clock frequency in range of 1MHz‐128MHz