DIRDA - versatile support for widely used IR transmission protocols.
Our efficient Core performs serial to parallel conversion on data received from an IR Receiver Diode. The processor can read the complete status of the DIRDA at any time during the functional operation. The DIRDA includes a programmable internal Prescaler which is able to divide a timing reference clock input by divisors of 1 to 128 and produce a clock for driving internal receiver logic. We also equipped our core with a processor interrupt system. Interrupts can be programmed according to your requirements, minimizing the computing required to handle the communications link. It can be provided with the small 8bit SRAM-like interface and APB slave interface. In MODE0 DIRDA decode the whole IR frame, and detect transmission errors and key release. In MODE1, internal FIFO is activated allowing 32 symbols to be stored during signal receive. Interrupt trigger level register may set any value from 1 to 32 symbols. All gathered makes it an ideal choice for prevalent IR protocols implementations like NEC, SIRC, TC9012 data format, or other non‐standard IR protocols.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Enabling and disabling controller via register
- Two working modes:
- MODE0 ‐ standard IR protocols decoding
- MODE1 ‐ symbols width detection for any standard or non‐standard IR data format
- Support for any configuration of the following protocols (MODE0):
- NEC with Simple Repeat Code
- NEC with Full Repeat Code
- TC9012 data format
- SIRC (SONY)
- Support for masked and not masked interrupts:
- Symbol overflow interrupt (MODE1)
- Symbol timeout interrupt (MODE1)
- Symbol received interrupt (MODE1)
- Key release interrupt (MODE0)
- Data overflow interrupt (MODE0)
- Data frame format error interrupt (MODE0)
- Data received interrupt (MODE0)
- Interrupts flags clearance via write to register
- Configurable reset
- Configurable data bus width
- Reference clock frequency in range of 1MHz‐128MHz
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