DP8051XP

The DP8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by the PMU – an advanced power management unit.
The DP8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051XP:

• Harvard, where internal data and program buses are separated, and
• von Neumann, with common program and external data bus

The DP8051XP has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051XP is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 8051 Cores has a built-in support for the proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

• Software in 100% compatible with 8051 industry standard
• Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
• Up to 14.632 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• 2 Data Pointers (DPTR) – for faster memory blocks copying
• Advanced INC & DEC modes
• Auto-switch of current DPTR
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
• Up to 8MB linear code space (in 80390 mode)
• Up to 16 MB of external (off-chip) Data Memory
• Synchronous eXternal Data Memory (SXDM) Interface
• User programmable Program Memory Wait States
• User programmable External Data Memory Wait States
• De-multiplexed Address/Data bus – to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available