DP80390

DP80390 8-bit MCU IP Core – High-Performance, Low-Power, Fully Customizable

The DP80390 is an ultra-high performance, speed-optimized 8-bit softcore MCU designed for both fast on-chip and slower off-chip memory systems. Supporting up to 8 MB of linear code space and 16 MB of linear data space, this softcore is engineered to deliver maximum performance while maintaining an excellent power-to-performance ratio, further enhanced by the advanced Power Management Unit (PMU).

Key Features & Configurations:

• 100% 8051 Binary Compatible: Ensures seamless integration with existing 8051-based software.

• Flexible Architecture Options:

  • Harvard – separate internal program and data buses for maximum throughput.

  • Von Neumann – shared program and external data bus for simplified memory design.

• Pipelined RISC Design: Executes 85–200 million instructions per second, offering 11–15× faster performance than a standard 80C51 at the same clock frequency.

• Low-Power Applications: The core can be clocked over ten times slower than the original 8051 without performance loss.

Advanced Peripheral & Debug Support:

• DoCD™ Real-Time Hardware Debugger: Non-intrusive debugging of a complete SoC. Supports halting, stepping, running, and memory/register inspection, including internal/external program memories, all SFRs, and user-defined peripherals.

• Comprehensive Test Bench: Delivered with a fully automated verification suite for easy integration and validation at all SoC design stages.

Applications: Ideal for embedded systems, IoT devices, industrial controllers, and any high-performance 8-bit 8051-based SoC requiring low power, extended memory, and advanced debugging capabilities.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• Software in 100% compatible with 80390 & 8051 industry standards
  • LARGE mode – 8051 instruction set
  • FLAT mode – 80390 instruction set
• Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
• Up to 14.632 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 8 MB of linear Program Memory
  • 64 kB of internal (on-chip) Program Memory
  • 8 MB external (off-chip) Program Memory
• Up to 16 MB of external (off-chip) Data Memory
• User programmable Program Memory Wait States
• User programmable External Data Memory Wait States
• De-multiplexed Address/Data bus, to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• 2 GHz virtual clock frequency in a 0.25u technological process
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available