DT8051

The DT8051 – area optimized, the tiny soft core of a single-chip 8-bit embedded microcontroller, based on the World’s fastest and most popular DP8051 core available for over 18 years. The DT8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. It has a very low gate count architecture, giving 6 650 ASIC gates for the complete system, including the DoCD on-chip debugger. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking the core vs 80C51, with the same settings. The DT8051 includes a 2-wire DoCD on-chip debugger (TTAG™), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART, and an interface for external SFR. The DT8051 Core has built-in support for the 2-wire TTAG™ interface – DCD’s Hardware Debug System, called DoCD™. This version of the debugger is dedicated to applications where the number of external pins is limited. The DT8051 is delivered with a fully automated test bench and complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, set breakpoints, and watchpoints, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. More details about our on-Chip Debugger

Watch the DT8051 presentation on DCD’s You Tube:

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• World’s smallest 8051 IP Core
• Software 100% compatible with the 8051 industry standard
• Very low gate count, area optimized architecture – 6 650 ASIC gates for complete system, including the DoCD on-chip debugger
• 8.1 times faster, than a standard 80C51 at the same frequency
• 7.63 VAX MIPS at 100 MHz
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
• Up to 64 kB of external (off-chip) Data Memory
• De-multiplexed Address/Data bus to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready