DP8051
The best combination of a die size and performance.
DP8051 Performance Chart
Description
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051:
- Harvard, where internal data and program buses are separated and
- von Neumann, with a common program and external data bus.
The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals.
DESIGN FEATURES:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Lattice,
- Microsemi / Microchip,
and others. - TSMC
- UMC
- SK Hynix
and others.
Key features
- Software in 100% compatible with 8051 industry standard
- Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
- Up to 14.632 VAX MIPS at 100 MHz
- 24 times faster multiplication
- 12 times faster division
- Up to 256 bytes of internal (on-chip) Data Memory
- Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
- Up to 8MB linear code space (in 80390 mode)
- Up to 16 MB of external (off-chip) Data Memory
- User programmable Program Memory Wait States
- User programmable External Data Memory Wait States
- De-multiplexed Address/Data bus – to allow easy memory connection
- Interface for additional Special Function Registers
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
Design | Dhry speed | on-chip CODE RAM/ROM | off-chip CODE | CODE write | IDATA space | XDATA space | XDATA, CODE wait states | DoCDTM | PMU | Interrupt sources | DPTR | Timers | UART | IO Ports | Compare/ Capture |
Watchdog | MDU MDU32 |
DI2CM | DI2CS | DSPI | DFPMU | DMAC | DCAN |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
DP80C51 | 11.46 | 64k/64k | 64k | 256 | 64k | 5 | 1 | 2 | 1 | 4 | |||||||||||||
DP8051XP | 15.55 | 64k/64k | 64k/8M | 256 | 16M | 15 | 2 | 3 | 2 | 4 | |||||||||||||
DP8051 | 15.36 | 64k/64k | 64k/8M | 256 | 16M | 5 | 1 | 2 | 1 | 4 | |||||||||||||
DP8051CPU | 15.36 | 64k/64k | 64k/8M | 256 | 16M | 2 | 1 | - | - | - | |||||||||||||
DQ8051XP | 29.01 | 64k/64k | 64k/8M | 256 | 16M | 15 | 2 | 3 | 2 | 4 | |||||||||||||
DQ8051 | 29.01 | 64k/64k | 64k/8M | 256 | 16M | 5 | 2 | 2 | 1 | 4 | |||||||||||||
DQ8051CPU | 28.40 | 64k/64k | 64k/8M | 256 | 16M | 2 | 2 | - | - | - | |||||||||||||
DT8051 | 8.11 | 64k/64k | 64k | 256 | 64k | 11 | 1 | 2 | 1 | 1 |
Features
DoCD Debugger
Power of Innovation is our primary target. That’s why our R&D focuses on every IP Core detail. As a result of that concern, some unique solutions were born. One of them is the on-Chip Debugger (DoCD™), which is a complete debugging system, dedicated for DCD's DQ80251/DQ8051/DT8051/DP8051x/DP80390x Microcontroller Cores.
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