DP8051

DP8051 – Ultra-High Performance 8-bit 8051 Softcore MCU

The DP8051 is an ultra-high performance, speed-optimized softcore of a single-chip 8-bit embedded controller, engineered to operate with both fast (on-chip) and slow (off-chip) memories. Designed with a strong focus on the performance-to-power-consumption ratio, it includes an advanced Power Management Unit (PMU) for optimized energy efficiency.

The DP8051 is 100% binary-compatible with the industry-standard 8051 microcontrollers and offers two flexible configurations:

• Harvard Architecture – separate internal program and data buses for maximum throughput.

• Von Neumann Architecture – shared program and external data bus for versatile integration.

Key Features & Capabilities:

• Pipelined RISC Architecture – Executes 120–300 million instructions per second for ultra-fast performance.

• Benchmark Performance – Dhrystone 2.1 runs 11.46–15.55× faster than the original 80C51 using the same compiler settings.

• Low-Power Applications – The core can operate over 10× slower than standard 8051 without performance loss, ideal for battery-powered or always-on systems.

• Fully Automated Validation – Delivered with a complete testbench and verification suite for seamless SoC integration.

• DoCD™ Debug Support – Built-in real-time hardware debugger providing non-intrusive SoC debugging, including CPU registers, program/data memory, and SFRs.

Ideal Applications:

Automotive electronics, industrial control systems, battery-powered embedded devices, and any SoC requiring high-speed, low-power 8051-compatible microcontrollers.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd.pl.

• Software in 100% compatible with 8051 industry standard
• Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
• Up to 14.632 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
• Up to 8MB linear code space (in 80390 mode)
• Up to 16 MB of external (off-chip) Data Memory
• User programmable Program Memory Wait States
• User programmable External Data Memory Wait States
• De-multiplexed Address/Data bus – to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available