DP80C51 Performance Chart

 80C51
 DT8051
 DP80C51
L1
L2
L3
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Description

The DP80C51 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management unit (PMU). The DP80C51 soft core is 100% binary and pin compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the DP80C51:

  • Harvard, where external data and program buses are separated, and
  • von Neumann, with common program and external data bus

The DP80C51 has a Pipelined RISC architecture (up to 10 times faster comparing to the standard architecture) and executes 85-200 million instructions per second. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP80C51 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 8051 Cores has a built-in support for the proprietary Hardware Debug System, called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals.

Key features

  • Pin in 100% compatible with industry standard 8051
  • Software in 100% compatible with industry standard 8051
  • Pipelined RISC architecture
  • 10 times faster, compared to 8051 standard
  • 24 times faster multiplication
  • 12 times faster division
  • Up to 256 bytes of internal (on-chip) Data Memory
  • Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory
  • Up to 64 kB of external (off-chip) Data Memory
  • User programmable Program Memory Wait States
  • User programmable External Data Memory Wait States
  • Dedicated signal for Program Memory writes
  • Interface for additional Special Function Registers
  • Fully synthesizable, static synchronous design, with positive edge clocking and no internal tri-states
  • Scan test ready
  • 2 GHz virtual clock frequency in a 0.25u technological process
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
Design Dhry speed on-chip CODE RAM/ROM off-chip CODE CODE write IDATA space XDATA space XDATA, CODE wait states DoCDTM PMU Interrupt sources DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DP80C51 11.46 64k/64k 64k 256 64k 5 1 2 1 4
DP8051XP 15.55 64k/64k 64k/8M 256 16M 15 2 3 2 4
DP8051 15.36 64k/64k 64k/8M 256 16M 5 1 2 1 4
DP8051CPU 15.36 64k/64k 64k/8M 256 16M 2 1 - - -
DQ8051XP 29.01 64k/64k 64k/8M 256 16M 15 2 3 2 4
DQ8051 29.01 64k/64k 64k/8M 256 16M 5 2 2 1 4
DQ8051CPU 28.40 64k/64k 64k/8M 256 16M 2 2 - - -
DT8051 8.11 64k/64k 64k 256 64k 11 1 2 1 1

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