DQ8051CPU

The DQ8051CPU is an ultra-high performance, speed-optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by an advanced power management unit – PMU. The DQ8051CPU softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. It has a built-in configurable DoCD-JTAG on-chip debugger, supporting Keil µVision development platform and a standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 26.67 to 29.01 times faster than the original 80C51 at the same frequency. This performance can be also exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, with no performance penalty. The DQ8051CPU is fully customizable – it is delivered in an exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The DQ8051CPU is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each of DCD’s 8051 cores has built-in support for DCD’s Hardware Debug System, called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Software is 100% compatible with 8051 industry standard
• Quad-Pipelined architecture enables to run 28.40 times faster, than the original 80C51 at the same frequency
• Up to 26.721 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• 2 Data Pointers (DPTR) – for faster memory blocks copying
  • Advanced INC & DEC modes
  • Auto-switch of current DPTR
• Up to 256 bytes of internal (on-chip) Data Memory – IDM
• Up to 64k bytes of Program Memory
• Up to 16 MB of external (off-chip) Data Memory – XDM
  • Synchronous interface – for up to 64K bytes of (on-chip) fast external Data Memory – (SXDM)
• User programmable Program Memory Wait States solution –  for wide range of memories’ speed
• User programmable External Data Memory Wait States solution – for wide range of memories’ speed
• De-multiplexed Address/Data bus – to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• No internal tri-states
• Scan test ready
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available