Description

The DQ8051CPU is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit – PMU. The DQ8051CPU soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. It has a built-in configurable DoCD-JTAG on-chip debugger, supporting Keil µVision development platform and a standalone DoCD debug software. Dhrystone 2.1 benchmark program runs from 26.67 to 29.01 times faster than the original 80C51 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, with no performance penalty. The DQ8051CPU is fully customizable – it is delivered in an exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The DQ8051CPU is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 8051 cores has a built-in support for DCD’s Hardware Debug System, called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals.

Key features

  • Software is 100% compatible with 8051 industry standard
  • Quad-Pipelined architecture enables to run 28.40 times faster, than the original 80C51 at the same frequency
  • Up to 26.721 VAX MIPS at 100 MHz
  • 24 times faster multiplication
  • 12 times faster division
  • 2 Data Pointers (DPTR) – for faster memory blocks copying
    • Advanced INC & DEC modes
    • Auto-switch of current DPTR
  • Up to 256 bytes of internal (on-chip) Data Memory – IDM
  • Up to 64k bytes of Program Memory
  • Up to 16 MB of external (off-chip) Data Memory – XDM
    • Synchronous interface – for up to 64K bytes of (on-chip) fast external Data Memory – (SXDM)
  • User programmable Program Memory Wait States solution –  for wide range of memories’ speed
  • User programmable External Data Memory Wait States solution – for wide range of memories’ speed
  • De-multiplexed Address/Data bus – to allow easy memory connection
  • Interface for additional Special Function Registers
  • Fully synthesizable
  • Static synchronous design
  • No internal tri-states
  • Scan test ready
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
Design Dhry speed on-chip CODE RAM/ROM off-chip CODE CODE write IDATA space XDATA space XDATA, CODE wait states DoCDTM PMU Interrupt sources DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DP80C51 11.46 64k/64k 64k 256 64k 5 1 2 1 4
DP8051XP 15.55 64k/64k 64k/8M 256 16M 15 2 3 2 4
DP8051 15.36 64k/64k 64k/8M 256 16M 5 1 2 1 4
DP8051CPU 15.36 64k/64k 64k/8M 256 16M 2 1 - - -
DQ8051XP 29.01 64k/64k 64k/8M 256 16M 15 2 3 2 4
DQ8051 29.01 64k/64k 64k/8M 256 16M 5 2 2 1 4
DQ8051CPU 28.40 64k/64k 64k/8M 256 16M 2 2 - - -
DT8051 8.11 64k/64k 64k 256 64k 11 1 2 1 1

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