DP80390CPU

DP80390CPU – High-Performance 8-bit Embedded Controller IP Core

The DP80390CPU is an ultra-high-performance, speed-optimized 8-bit soft microcontroller IP core, designed for single-chip embedded SoC implementations operating with both fast on-chip memories and slower off-chip memory devices. The core is optimized for an exceptional performance-to-power-consumption ratio, making it ideal for low-power, cost-sensitive, and performance-critical embedded applications.

The architecture supports up to 8 MB of linear program (code) space and 16 MB of linear data space, significantly extending the addressing capabilities beyond traditional 8051-based designs. Power efficiency is further enhanced by an advanced Power Management Unit (PMU), enabling aggressive clock scaling without loss of performance.

100% Binary Compatibility with 80390 / 8051

DP80390CPU is fully binary-compatible with the industry-standard 80390 and 8051 8-bit microcontroller architectures, allowing seamless reuse of existing firmware, toolchains, and legacy software investments.

Flexible System Architectures

The core is available in two architectural configurations to match different SoC integration strategies:

• Harvard Architecture – separate internal program and data buses for maximum throughput

• von Neumann Architecture – shared program and external data bus for simplified system design

High-Performance Pipelined RISC Architecture

DP80390CPU features a pipelined RISC microarchitecture, delivering performance levels far exceeding classic 8-bit MCUs:

• 85 to 200 MIPS, depending on configuration and target frequency

• Dhrystone 2.1 performance: 11.46× to 15.55× faster than the original 80C51 running at the same clock frequency

• Benchmarked using the same C compiler and identical compilation settings, ensuring fair and reproducible results

This performance headroom can be directly leveraged in ultra-low-power designs, where the core may be clocked over 10× slower than legacy implementations while maintaining equivalent application performance.

SoC-Ready Verification and Debug Support

The DP80390CPU is delivered with a fully automated testbench and a comprehensive regression test suite, enabling fast IP qualification and validation across all stages of the SoC design flow.

Each DP80390CPU core includes built-in support for DoCD™ (Digital Core Design on-Chip Debugger) — a proprietary real-time hardware debug system providing non-intrusive debugging of a live SoC. Unlike traditional on-chip debuggers, DoCD™ allows full system visibility without disturbing application execution.

DoCD™ capabilities include:

• Run, halt, single-step, step-over, and instruction skipping

• Read/write access to all registers, SFRs, and user-defined peripherals

• Full visibility into internal and external program and data memories

• True non-intrusive debugging of real-time embedded systems

Key Benefits for Design Engineers

• Drop-in 80390 / 8051 software compatibility

• Up to 200 MIPS performance in an 8-bit MCU class

• Advanced PMU for low-power SoC designs

• Harvard or von Neumann architecture options

• Proven Dhrystone benchmark leadership

• Non-intrusive, system-wide hardware debugging

• SoC-ready delivery with automated verification

DP80390CPU vs. Classic 8051 Microcontroller

🏭 Industrial Systems

Designed for industrial control, automation, and field devices, DP80390CPU delivers deterministic real-time performance with long product lifecycle support. High execution efficiency allows lower clock frequencies, reducing power dissipation and EMI, while full 8051 software compatibility protects legacy codebases commonly used in industrial environments.

Ideal for:

• PLC subsystems

• Motor control

• Industrial gateways

• Fieldbus and sensor aggregation SoCs

🚗 Automotive Electronics

DP80390CPU is well-suited for automotive body, comfort, and monitoring systems, where predictable behavior, low power, and proven architectures are essential. The core enables reuse of certified 8051-based software while providing significantly higher performance headroom for next-generation automotive SoCs.

Ideal for:

• Body control modules (BCM)

• Lighting and climate controllers

• Automotive sensor hubs

• Mixed-signal automotive ASICs

🌐 IoT and Edge Devices

For IoT nodes and edge devices, DP80390CPU combines ultra-low-power operation with enough performance to handle communication stacks, security functions, and sensor processing. Clock-scaling enabled by its high MIPS efficiency makes it especially effective in battery-powered and energy-harvesting designs.

Ideal for:

• IoT gateways

• Smart sensors

• Wearables and metering

• Edge AI companion controllers

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com

• Software in 100% compatible with 80390 & 8051 industry standards
  • LARGE mode – 8051 instruction set
  • FLAT mode – 80390 instruction set
• Pipelined RISC architecture enables to run 15.55 times faster, than the original 80C51 at the same frequency
• Up to 14.632 VAX MIPS at 100 MHz
• 24 times faster multiplication
• 12 times faster division
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 8 MB of linear Program Memory
  • 64 kB of internal (on-chip) Program Memory
  • 8 MB external (off-chip) Program Memory
• Up to 16 MB of external (off-chip) Data Memory
• User programmable Program Memory Wait States
• User programmable External Data Memory Wait States
• De-multiplexed Address/Data bus, to allow easy memory connection
• Interface for additional Special Function Registers
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• 2 GHz virtual clock frequency in a 0.25u technological process
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available